diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-12-19 18:02:17 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-03-24 04:01:11 +0000 |
| commit | cf32fd172928467ac5bbd4fb372b71230c81cf12 (patch) | |
| tree | 9680154700a8d442e9f41d271ac208a6e28ecedf /src/mainboard | |
| parent | 10f5ccf9cb26e58aaaf7d77813bf43b235eea4af (diff) | |
soc/intel/common: Remove common chip config use_fsp_mp_init
This patch ensures to make use of common MP Init Kconfig to
choose desire method to peform MP initialization for platform.
Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/saddlebrook/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/saddlebrook/devicetree.cb | 5 |
2 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 524bcca011..f2b7344aaa 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS select SADDLEBROOK_USES_FSP1_1 select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION + select USE_INTEL_FSP_MP_INIT config SADDLEBROOK_USES_FSP1_1 bool "FSP driver 1.1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 8f78249b3b..2f84a5dde5 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -140,11 +140,6 @@ chip soc/intel/skylake .voltage_limit = 0x5F0 \ }" - # Skip coreboot MP Init - register "common_soc_config" = "{ - .use_fsp_mp_init = 1, - }" - # Enable x1 slot register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" |