emulation/qemu-q35: Use MMCONF_SUPPORT_DEFAULT

Change all PCI configuration accesses to MMIO in qemu-q35
emulation

To enable MMIO style access, add (move) explicit PCI IO config write
in the bootblock. As there is no northbridge/x/x/bootblock.c
file, a mainboard/x/x/bootblock.c file is added for this purpose.

Change-Id: I979efb3d9b2f359a9ccbd1b4f6c05f83bab43007
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3599
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

3 files changed, 43 insertions, 5 deletions

diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index 7f33699001..9d78bb8bf4 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOUTHBRIDGE_INTEL_I82801IX
 	select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
 	select MMCONF_SUPPORT
+	select MMCONF_SUPPORT_DEFAULT
 	select CACHE_AS_RAM
 #	select HAVE_OPTION_TABLE
 #	select HAVE_PIRQ_TABLE
@@ -24,10 +25,18 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "QEMU x86 q35/ich9"
 
+config BOOTBLOCK_MAINBOARD_INIT
+	string
+	default "mainboard/emulation/qemu-q35/bootblock.c"
+
 #config IRQ_SLOT_COUNT
 #	int
 #	default 6
 
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xb0000000
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xd0000
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
new file mode 100644
index 0000000000..939a4e6320
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -0,0 +1,33 @@
+#include <arch/io.h>
+
+/* Just define these here, there is no gm35.h file to include. */
+#define D0F0_PCIEXBAR_LO 0x60
+#define D0F0_PCIEXBAR_HI 0x64
+
+static void bootblock_northbridge_init(void)
+{
+	uint32_t reg;
+
+	/*
+	 * The "io" variant of the config access is explicitly used to
+	 * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+	 * to true. That way all subsequent non-explicit config accesses use
+	 * MCFG. This code also assumes that bootblock_northbridge_init() is
+	 * the first thing called in the non-asm boot block code. The final
+	 * assumption is that no assembly code is using the
+	 * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+	 *
+	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
+	 * 4GiB.
+	 */
+	reg = 0;
+	pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg);
+	reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */
+	pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg);
+}
+
+static void bootblock_mainboard_init(void)
+{
+	bootblock_northbridge_init();
+	bootblock_southbridge_init();
+}
diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c
index 3740064a80..78c92a9b38 100644
--- a/src/mainboard/emulation/qemu-q35/mainboard.c
+++ b/src/mainboard/emulation/qemu-q35/mainboard.c
@@ -27,7 +27,6 @@
 #include <console/console.h>
 
 #define Q35_PAM0            0x90
-#define Q35_PCIEXBAR_ADDR   0xb0000000
 
 static const unsigned char qemu_q35_irqs[] = {
 	10, 10, 11, 11,
@@ -59,9 +58,6 @@ static void qemu_nb_init(device_t dev)
 	/* setup IRQ routing southbridge devices */
 	for (i = 25; i < 32; i++)
 		pci_assign_irqs(0, i, qemu_q35_irqs);
-
-	/* setup mmconfig */
-	pci_write_config32(dev, 0x60, Q35_PCIEXBAR_ADDR | 1);
 }
 
 static void qemu_nb_read_resources(struct device *dev)
@@ -69,7 +65,7 @@ static void qemu_nb_read_resources(struct device *dev)
 	pci_dev_read_resources(dev);
 
 	/* reserve mmconfig */
-	fixed_mem_resource(dev, 2, Q35_PCIEXBAR_ADDR >> 10, 0x10000000 >> 10,
+	fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10,
 			   IORESOURCE_RESERVE);
 }