diff options
| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2017-06-05 12:33:23 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-06-07 12:04:50 +0200 |
| commit | a8843dee58d15de6860b682975ee01ee61893670 (patch) | |
| tree | f26fe56b7ddf2452dadd6a9de88819d789410f91 /src/mainboard | |
| parent | 619e83045a3dfc189cf12b2f755b7a888c428382 (diff) | |
Use more secure HTTPS URLs for coreboot sites
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/README | 2 | ||||
| -rw-r--r-- | src/mainboard/via/epia-m700/romstage.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README index 1d7bbdc822..ffcbcc021f 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/README +++ b/src/mainboard/supermicro/h8dmr_fam10/README @@ -17,6 +17,6 @@ while. Again, not an issue specific to this port. * to avoid very slow LZMA decompression I use this port with LZMA compression disabled in CBFS. I'm not sure what's causing this particular slowness. -See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html +See also this thread: https://www.coreboot.org/pipermail/coreboot/2009-September/052107.html Ward, 2009-09-22 diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 7b7140e105..f59eedb367 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -46,7 +46,7 @@ /* * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: - * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. + * https://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. */ static int acpi_is_wakeup_early_via_vx800(void) { @@ -527,7 +527,7 @@ void main(unsigned long bist) #if PAYLOAD_IS_SEABIOS == 1 if (boot_mode == 3) { /* An idea of Libo.Feng at amd.com in - * http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html + * https://www.coreboot.org/pipermail/coreboot/2008-December/043111.html * * I want move the 1M data, I have to set some MTRRs myself. * Setting MTRR before back memory save s3 resume time about |