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authorTim Wawrzynczak <twawrzynczak@chromium.org>2019-09-18 11:22:56 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-09-20 07:16:44 +0000
commit954111695cb7e27647ed9c150cac2f77d39c1e09 (patch)
treedac2711d908f9c95ba5aa87c6ce1cce2de388c36 /src/mainboard
parent7f7ab8f16cd6524d0d0fd29141decdc32bc14182 (diff)
mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configuration
A closer read of the EDS indicates that when GPIO Driver mode is selected, GPIO input event updates are limited to GPI_STS only. GPI_GPE_STS updates are therefore masked, and we don't want to enable this behavior. It masks the GPE and does not allow us to see this GPE as a wake source, obscuring the reason that the system woke up. Also switch the IRQ from level-triggered to edge-triggered, otherwise the system will auto-wake from any sleep state when the pen is ejected from the garage. BUG=b:132981083 BRANCH=none TEST=Wake up system from S0ix using pen eject, verify that mosys eventlog shows GPE#8 as the S0ix wakeup source. Wake up system from S3 via pen eject, and verify that the wakeup source shows as GPE#8. Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35459 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/gpio.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index fcb1a614cc..240bb5d23b 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -31,7 +31,7 @@ static const struct pad_config gpio_table[] = {
/* A7 : PP3300_SOC_A */
PAD_NC(GPP_A7, NONE),
/* A8 : PEN_GARAGE_DET_L (wake) */
- PAD_CFG_GPI_GPIO_DRIVER_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE),
+ PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE),
/* A9 : ESPI_CLK */
/* A10 : FPMCU_PCH_BOOT1 */
PAD_CFG_GPO(GPP_A10, 0, DEEP),