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authorJes Klinke <jbk@google.com>2020-10-30 13:23:14 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-11-04 09:37:42 +0000
commit5c7311a5248ee2e021a163d49234d5412fba6ad4 (patch)
treed46f66020e60f79f4dce256a2b30b66d3590e8cd /src/mainboard
parentb5f580e03c8797278bebec66f30eeae6bf41fab8 (diff)
mb/google/volteer: clang-format mainboard.c
This CL is entirely generated by running the automatic formatter on this one file. BUG=None TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214 Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/volteer/mainboard.c17
1 files changed, 7 insertions, 10 deletions
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index 016572a39f..acba9722dc 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -102,8 +102,7 @@ void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg)
return;
}
- if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) &&
- cr50_is_long_interrupt_pulse_enabled()) {
+ if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) {
printk(BIOS_INFO, "Enabling S0i3.4\n");
} else {
/*
@@ -126,8 +125,7 @@ static void mainboard_chip_init(void *chip_info)
base_pads = variant_base_gpio_table(&base_num);
override_pads = variant_override_gpio_table(&override_num);
- gpio_configure_pads_with_override(base_pads, base_num,
- override_pads, override_num);
+ gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
}
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
@@ -135,14 +133,13 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
bool has_usb4;
/* If device doesn't have USB4 hardware, disable tbt */
- has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) ||
- fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)));
+ has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2))
+ || fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)));
if (!has_usb4)
- memset(params->ITbtPcieRootPortEn,
- 0,
- ARRAY_SIZE(params->ITbtPcieRootPortEn) *
- sizeof(*params->ITbtPcieRootPortEn));
+ memset(params->ITbtPcieRootPortEn, 0,
+ ARRAY_SIZE(params->ITbtPcieRootPortEn)
+ * sizeof(*params->ITbtPcieRootPortEn));
}
struct chip_operations mainboard_ops = {