diff options
author | Marc Jones <marc.jones@se-eng.com> | 2012-02-21 17:53:13 -0700 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-02-22 11:35:17 +0100 |
commit | fff8cdfcdeedb3723bd9dba66e19ae1a56ba9c8f (patch) | |
tree | 1589a3135ec4dbe3e3166350969357a154f536c1 /src/mainboard | |
parent | 0864016b0d5d9d7e54f120873282967759886d95 (diff) |
Remove old AMD fam10 fixme comment
The family10 code had a very slow decompress before the cache settings were
fixed. This has been fixed for some time. Remove all the old messages from the
serial stream.
Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/672
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/amd/mahogany_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/amd/tilapia_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/asus/m4a78-em/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/asus/m4a785-m/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/gigabyte/ma785gmt/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/gigabyte/ma78gm/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/jetway/pa78vm5/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/msi/ms9652_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/tyan/s2912_fam10/romstage.c | 1 |
13 files changed, 0 insertions, 13 deletions
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 04a9e45a57..dce9baabd3 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -220,7 +220,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index b41230dece..29b00b27d4 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -331,7 +331,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("After MCT init before CAR disabled."); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 52cab42eb4..f316395e27 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -220,7 +220,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 76449cbcdf..a96592d20c 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -221,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 76449cbcdf..a96592d20c 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -221,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 4572169b87..68f3dcc3b1 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index bd81e67733..6c25a9e79d 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -219,7 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 54b364ae23..f51b3ece72 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -222,7 +222,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index b2d4ecba03..ba3b2084d2 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -227,7 +227,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index fc8120b8a2..0bf6d114be 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -241,7 +241,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index c9fb928a6d..4e243c284e 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -240,7 +240,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 post_code(0x42); // Should never see this post code. } diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 870125dd1f..d9d5218bb8 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -290,7 +290,6 @@ post_code(0x40); raminit_amdmct(sysinfo); post_code(0x41); -// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x42); // Should never see this post code. } diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 97c03b59df..df571a0d13 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -238,7 +238,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } |