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authorKyösti Mälkki <kyosti.malkki@gmail.com>2022-11-28 12:37:17 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2022-11-30 04:05:55 +0000
commitf2b9852a8e583bf7d485541152782f2a1ba0d49e (patch)
treedcec312f9cf01b283785ce13f9730f516dffd957 /src/mainboard
parent8b8ada6fdb3ebab672571c581eed3a7285589d83 (diff)
nb/intel/e7505: Hook up PCI domain and CPU ops to devicetree
Change-Id: I70fb470b63ddd06f1d1e34deaea296d81e24f75f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70058 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/aopen/dxplplusu/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb
index 2dfa03d873..df99751c33 100644
--- a/src/mainboard/aopen/dxplplusu/devicetree.cb
+++ b/src/mainboard/aopen/dxplplusu/devicetree.cb
@@ -3,9 +3,11 @@
chip northbridge/intel/e7505
device cpu_cluster 0 on
+ ops e7505_cpu_bus_ops
end
device domain 0 on
+ ops e7505_pci_domain_ops
device pci 0.0 on end # Chipset host controller
device pci 0.1 on end # Host RASUM controller
device pci 2.0 on # Hub interface B