diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2019-01-14 13:57:50 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-23 14:44:23 +0000 |
| commit | ea415b335f57bde8e744e0f40845cc6fdd671c71 (patch) | |
| tree | 2838505d071bf1ee9998160244e4040e36e80434 /src/mainboard | |
| parent | 4865fe97d9afe113efb4f86d305cf404ed26f8b4 (diff) | |
mediatek/mt8183: Add Micron 4GB LPDDR4X DDR support
BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test pass on Kukui.
Change-Id: I985c5061ce4ed4d88a17619aa5cde7d0121dd3a3
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/mainboard')
3 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 25bbe8ffe2..cbfb08d5ce 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -20,6 +20,7 @@ static const char *const sdram_configs[] = { [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", }; static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index d15c40dd03..1e11140873 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,5 +1,6 @@ sdram-params := sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB +sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c new file mode 100644 index 0000000000..0fb5abacba --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/emi.h> + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x5, 0x7, 0x0, 0xF}, + [ODT_ON] = {0x6, 0x9, 0x0, 0xF} + }, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; |