diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-13 14:54:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-18 12:09:40 +0000 |
| commit | e912e3ee567672871a98e3d2618d804fca4a7cb6 (patch) | |
| tree | e40cbb99e7f42d4a564ae60981793b0b414bfefc /src/mainboard | |
| parent | 9c6936980517964f5e3013df685a6e4913b1a073 (diff) | |
src: Remove unneded whitespace before tab
Also remove unneded tab in 'picasso/Makefile.c' file.
Change-Id: Id25b2d308645c449c205b3a946f89b6b6de62a47
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x230/variants/x230s/overridetree.cb | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb index 541db02be6..77d3bb0419 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb @@ -3,8 +3,8 @@ chip northbridge/intel/i440bx # Northbridge chip southbridge/intel/i82371eb # Southbridge register "gpo" = "0x7fbfb9ff" register "gpo22_enable" = "1" # GPO22 controls LVD port termination (0=enabled) - # GPO23 controls SCSI-50 port termination (1=enabled) - # SCSI-68 port is always terminated + # GPO23 controls SCSI-50 port termination (1=enabled) + # SCSI-68 port is always terminated device pci 4.0 on # ISA bridge chip superio/winbond/w83977tf # Super I/O device pnp 3f0.a off # ACPI diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb index 6d37aabc01..9e9d956935 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -8,7 +8,7 @@ chip northbridge/intel/sandybridge register "gpu_panel_port_select" = "1" # eDP register "gpu_panel_power_backlight_off_delay" = "1" # 0.1ms register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms - register "gpu_panel_power_down_delay" = "500" # 50ms + register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_up_delay" = "2000" # 200ms device domain 0 on |