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authorSebastian 'Swift Geek' Grzywna <swiftgeek@gmail.com>2021-09-01 08:08:23 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-09-07 14:22:06 +0000
commite277d0807f57ffbeed7bac5916efa15b5a6a83a6 (patch)
tree96230a093e70562d952d305057ddd93109ae8942 /src/mainboard
parent5e3854ae7b585d798974eb649ca9e6088b54debf (diff)
mb/asrock/e350m1: Enable USB on mPCIe
Verified by running following on vendor and observing mPCIe USB device (dis)appearing: echo 1 > /sys/bus/pci/devices/0000:00:16.0/remove echo 1 > /sys/bus/pci/devices/0000:00:16.2/remove echo 1 > /sys/bus/pci/devices/0000:00:00.0/rescan Change-Id: I6ee7e3679c9cd87b81f955c68ec89db1dda30aec Signed-off-by: Sebastian 'Swift Geek' Grzywna <swiftgeek@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/asrock/e350m1/devicetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index c1740dce2b..1fb8b20ca4 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -92,8 +92,8 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 15.1 on end # PCIe PortB: NIC
device pci 15.2 on end # PCIe PortC: USB3
device pci 15.3 off end # PCIe PortD
- device pci 16.0 off end # OHCI USB3
- device pci 16.2 off end # EHCI USB3
+ device pci 16.0 on end # OHCI mPCIe
+ device pci 16.2 on end # EHCI mPCIe
# gpp_configuration options
#0000: PortA lanes[3:0]