diff options
| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-08 12:29:23 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-09 19:08:40 +0000 |
| commit | dcce5a33e95b1fa3c09a0ab0a9e951336cbf096e (patch) | |
| tree | 78f59c4862137cc3050d7908643fe4d56558e7b3 /src/mainboard | |
| parent | 66ff4fb1a565fe5f040e893bd02e52fed3ad2771 (diff) | |
mb/google/kahlee: enable uart0 for console in devicetree
Kahlee selects AMD_SOC_CONSOLE_UART causing UART0 to be used as console,
so enable uart_0 in the devicetree to make sure that the UART will be
marked as enabled in the SSDT that will be generated with the next patch
applied. This also matches the other AMD SoC based Chromebooks.
Change-Id: Ibe18f87d8bf63603fb2eb87728395e45e9a9ef69
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77094
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb index 632ffa3e9a..92c0d14803 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -109,4 +109,7 @@ chip soc/amd/stoneyridge device i2c 10 on end end end + + device ref uart_0 on end # console + end #chip soc/amd/stoneyridge |