diff options
| author | zhourui <zhourui@huaqin.corp-partner.google.com> | 2022-11-21 14:44:39 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-11-30 07:56:29 +0000 |
| commit | d892a336bbf6678adb83a5b6f48f13dea64f45eb (patch) | |
| tree | 879c73ed6ed2f437ed7a74d721ac48d97c6cabfe /src/mainboard | |
| parent | f2b9852a8e583bf7d485541152782f2a1ba0d49e (diff) | |
mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4
This change disables unused PCIE RP8 and CLKSRC4. Without this change
sasukette cannot enter into s0ix properly.
BUG=b:259891452
TEST=Build and verified in sasukette
Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/dedede/variants/sasukette/overridetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 1cda193268..43a68dbb16 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -8,6 +8,10 @@ fw_config end chip soc/intel/jasperlake + # Disable PCIe Root Port 8 (index 7) + register "PcieRpEnable[7]" = "0" + # Disable PCIe Clock Source 4 (index 3) + register "PcieClkSrcUsage[3]" = "0xff" # Intel Common SoC Config #+-------------------+---------------------------+ |