diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-13 14:34:10 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-10 16:01:20 +0000 |
| commit | c666a916112aece345da57a0b4f3bafc43234ee7 (patch) | |
| tree | 59cfab421bd92ff5635aa651a9062779bc0d3fbf /src/mainboard | |
| parent | 4da9d6b41d08e58e0e8a868acd76cedfb1b54586 (diff) | |
soc/amd/genoa: Enable eSPI early
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/onyx/devicetree.cb | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb index 5f447b2540..2b37b761fd 100644 --- a/src/mainboard/amd/onyx/devicetree.cb +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -1,5 +1,18 @@ chip soc/amd/genoa + # eSPI configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN, + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + device domain 0 on end |