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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2024-03-08 16:17:45 +0800
committerMartin L Roth <gaumless@gmail.com>2024-03-11 16:00:04 +0000
commitc4e68f6080a3ca0f678efce14d778b5602120865 (patch)
tree029441b9e7a2ac50fcc861526a34b4a7cb3a7f9b /src/mainboard
parent7c58dd6ce898dd6b10c244849fefb710983154f2 (diff)
mb/google/brya: Create nova variant
Create the nova variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:328711879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOVA Change-Id: Ie1cee43f0e2545288130bcc5152075603695c395 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/brya/Kconfig7
-rw-r--r--src/mainboard/google/brya/Kconfig.name3
-rw-r--r--src/mainboard/google/brya/variants/nova/include/variant/ec.h8
-rw-r--r--src/mainboard/google/brya/variants/nova/include/variant/gpio.h8
-rw-r--r--src/mainboard/google/brya/variants/nova/overridetree.cb6
5 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index b85aa5abad..bf0825d837 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -331,6 +331,10 @@ config BOARD_GOOGLE_NEREID
config BOARD_GOOGLE_NOKRIS
select BOARD_GOOGLE_BASEBOARD_NISSA
+config BOARD_GOOGLE_NOVA
+ select BOARD_GOOGLE_BASEBOARD_BRASK
+ select SOC_INTEL_RAPTORLAKE
+
config BOARD_GOOGLE_OMNIGUL
select BOARD_GOOGLE_BASEBOARD_BRYA
select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -597,6 +601,7 @@ config DRIVER_TPM_I2C_BUS
default 0x0 if BOARD_GOOGLE_ANRAGGAR
default 0x1 if BOARD_GOOGLE_XOL
default 0x0 if BOARD_GOOGLE_GLASSWAY
+ default 0x1 if BOARD_GOOGLE_NOVA
config DRIVER_TPM_I2C_ADDR
hex
@@ -681,6 +686,7 @@ config MAINBOARD_PART_NUMBER
default "Anraggar" if BOARD_GOOGLE_ANRAGGAR
default "Xol" if BOARD_GOOGLE_XOL
default "Glassway" if BOARD_GOOGLE_GLASSWAY
+ default "Nova" if BOARD_GOOGLE_NOVA
config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
@@ -736,6 +742,7 @@ config VARIANT_DIR
default "anraggar" if BOARD_GOOGLE_ANRAGGAR
default "xol" if BOARD_GOOGLE_XOL
default "glassway" if BOARD_GOOGLE_GLASSWAY
+ default "nova" if BOARD_GOOGLE_NOVA
config VBOOT
select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index bea92b6676..c126558909 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -160,3 +160,6 @@ config BOARD_GOOGLE_ZYDRON
config BOARD_GOOGLE_XOL
bool "-> Xol"
+
+config BOARD_GOOGLE_NOVA
+ bool "-> Nova"
diff --git a/src/mainboard/google/brya/variants/nova/include/variant/ec.h b/src/mainboard/google/brya/variants/nova/include/variant/ec.h
new file mode 100644
index 0000000000..7a2a6ff8b7
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nova/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/nova/include/variant/gpio.h b/src/mainboard/google/brya/variants/nova/include/variant/gpio.h
new file mode 100644
index 0000000000..c4fe342621
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nova/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb
new file mode 100644
index 0000000000..4f2c04a57a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/nova/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ end
+
+end