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author | Ian Feng <ian_feng@compal.corp-partner.google.com> | 2023-04-28 13:32:16 +0800 |
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committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-05-12 14:52:16 +0000 |
commit | b757a67ae1bc7e80fa6b16d77fafa9467be33a51 (patch) | |
tree | d86f933fd566f847300d16ef806e00a7ce2e4a43 /src/mainboard | |
parent | a4298bc3f82f476ce82e3e948f6573f5e38dfb25 (diff) |
mb/google/nissa/var/uldren: Fix Touch screen power sequence
Based on touchscreen product spec.
For uldren variants with a touchscreen, drive the enable GPIO high
starting in romstage while holding in reset, then disable the reset
GPIO in ramstage (done in the baseboard).
BUG=b:279989974
TEST=Build and boot to OS in uldren. Touch screen is workable.
Change-Id: Ib1b1ce80aa1dd8c312e3663fc50c9e9f53cc07fe
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74835
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/google/brya/variants/uldren/gpio.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/uldren/gpio.c b/src/mainboard/google/brya/variants/uldren/gpio.c index 9c427f64e7..e1e5e8cd4d 100644 --- a/src/mainboard/google/brya/variants/uldren/gpio.c +++ b/src/mainboard/google/brya/variants/uldren/gpio.c @@ -17,6 +17,8 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_B6, NONE), /* B15 : HP_RST_ODL */ PAD_CFG_GPO(GPP_B15, 1, DEEP), + /* C1 : SMBDA==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), /* D6 : SRCCLKREQ1# ==> WWAN_EN */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* D8 : SRCCLKREQ3# ==> NC */ @@ -76,6 +78,11 @@ static const struct pad_config early_gpio_table[] = { }; static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) |