diff options
| author | Joey Peng <joey.peng@lcfc.corp-partner.google.com> | 2022-01-24 16:16:15 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 18:05:15 +0000 |
| commit | b65c3015b0c931b8ad7897a9835798cd97dbcf5b (patch) | |
| tree | d3a3ba4da113b47a52a3f9f5b8d3765307459325 /src/mainboard | |
| parent | 51ede8af2e95734c7f7e820f7a29409fbb3c0605 (diff) | |
mb/google/brya/var/taniks: Modify DPTF settings for taniks
Update DPTF settings provided by thermal team
BUG=b:215033682
TEST=build and tested on taniks board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic6860980b06e876dd4c21af26752ab6c1a3f7fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/taniks/overridetree.cb | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index e6ceca19fc..26a419517a 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -127,31 +127,31 @@ chip soc/intel/alderlake [1] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), + TEMP_PCT(57, 70), + TEMP_PCT(54, 60), + TEMP_PCT(48, 60), TEMP_PCT(45, 45), - TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(42, 39), } }, [2] = { .target = DPTF_TEMP_SENSOR_2, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), + TEMP_PCT(57, 40), + TEMP_PCT(54, 60), + TEMP_PCT(48, 60), TEMP_PCT(45, 45), - TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(42, 39), } }, [3] = { .target = DPTF_TEMP_SENSOR_3, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), + TEMP_PCT(57, 70), + TEMP_PCT(54, 60), + TEMP_PCT(48, 60), TEMP_PCT(45, 45), - TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(42, 39), } } }" @@ -177,7 +177,7 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { .min_power = 3000, - .max_power = 12000, + .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, @@ -204,11 +204,11 @@ chip soc/intel/alderlake [0] = { 100, 6000, 220, 2200, }, [1] = { 92, 5500, 180, 1800, }, [2] = { 85, 5000, 145, 1450, }, - [3] = { 74, 4620, 115, 1150, }, - [4] = { 60, 4290, 90, 900, }, - [5] = { 45, 3980, 55, 550, }, - [6] = { 35, 3170, 30, 300, }, - [7] = { 30, 2640, 15, 150, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 60, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 39, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, [8] = { 10, 800, 10, 100, }, [9] = { 0, 0, 0, 50, } }" |