diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-08-02 12:44:19 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-08-03 07:46:10 +0000 |
| commit | b256e6303c13abc13825bf2d3fb2fbc2ed1fd788 (patch) | |
| tree | 0a918a43d90b2282f9cf8e2ec262209e43f274e6 /src/mainboard | |
| parent | 6886a62132de38594a5078d5f3192ceed34576f0 (diff) | |
mb/google/rex: Skip UART0 config in FSP
UART0 is already configured in coreboot, so this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in FSP.
BUG=none
TEST=Able to build and boot google/rex0. Able to see all debug prints
over CPU uart.
Change-Id: I37744f05083eb82ba8ca579b628b69aa976e3d1f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83750
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 1a80e2aecb..00acbecc3e 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -73,7 +73,7 @@ chip soc/intel/meteorlake register "skip_ext_gfx_scan" = "1" register "serial_io_uart_mode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" |