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authorSean Rhodes <sean@starlabs.systems>2022-06-16 22:44:41 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-06-20 12:11:01 +0000
commitb02c90d146f4929acdee0f28e4c0ddd545ffdb04 (patch)
tree700d09cae0ac0a8de4789f95063ee0be2c841ff5 /src/mainboard
parent8a1eb1993d9e48305a82b670c34bafefa9730594 (diff)
mb/starlabs/lite/glkr: Correct the daughterboard USB 3.0 port number
The daughterboard USB 3.0 was set to port 3, which is incorrect. This patch corrects that to port 4. This fixes an issue where USB 3.0 devices are not detected when plugged in to this port. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50f86dee1b512d0dd20d07e3ee17ebfa5e537bc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/starlabs/lite/variants/glkr/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
index 057fc2b51a..aad20ea8f6 100644
--- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
@@ -100,7 +100,7 @@ chip soc/intel/apollolake
# Daughterboard SD Card
register "usb2_port[5]" = "PORT_EN(OC_SKIP)"
- register "usb3_port[3]" = "PORT_EN(OC1)"
+ register "usb3_port[4]" = "PORT_EN(OC1)"
# Bluetooth
register "usb2_port[6]" = "PORT_EN(OC_SKIP)"