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authorDan Callaghan <dcallagh@google.com>2021-10-28 21:26:12 +1100
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-10-28 23:11:55 +0000
commitb00bfd076502add705c894711b3b954a0d07d909 (patch)
treeb8c69405a22cefbc5f1829fd9ad6fd0a748df47d /src/mainboard
parent59a348b75a43d41411dfd7fc4f5d6d1f26404381 (diff)
mb/google/brya/var/taeko: add HPS as generic I2C peripheral
BUG=b:202784200 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Dan Callaghan <dcallagh@google.com> Change-Id: I400719d762b001811f809f9549fd030dff9928d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/brya/variants/taeko/overridetree.cb19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 6806d8b3a0..57c9cead30 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -35,6 +35,10 @@ fw_config
option BOOT_EMMC_DISABLED 0
option BOOT_EMMC_ENABLED 1
end
+ field HPS 17
+ option HPS_ABSENT 0
+ option HPS_PRESENT 1
+ end
end
chip soc/intel/alderlake
register "TcssAuxOri" = "1"
@@ -276,6 +280,21 @@ chip soc/intel/alderlake
device i2c 10 on end
end
end
+ device ref i2c2 on
+ chip drivers/i2c/generic
+ register "hid" = ""GOOG0020""
+ register "desc" = ""Chrome OS HPS""
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
+ # HPS uses I2C addresses 0x30 and 0x51.
+ # The address we provide here is not significant because
+ # neither coreboot nor Linux have a driver for HPS,
+ # it's only used from userspace.
+ device i2c 30 on
+ probe HPS HPS_PRESENT
+ end
+ end
+ end
device ref i2c5 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""