diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-03-25 15:31:12 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-01 16:39:28 +0000 |
| commit | a23e0c9d74b7f06738ebf28b068e1bd63f246982 (patch) | |
| tree | 5afd6c3027ebca12e4d6f94b443fe42dd1f3b75e /src/mainboard | |
| parent | 51ce41c0e661fd9cb9207463bcbd920e55b44a62 (diff) | |
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop
referring from soc/intel/tigerlake.
Addtionally mainboard changes are done to support build.
BUG=b:150217037
TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board.
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard')
11 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 53423b8cb9..98ef6e49cc 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -18,7 +18,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include <soc/intel/tigerlake/acpi/platform.asl> + #include <soc/intel/jasperlake/acpi/platform.asl> /* global NVS and variables */ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> @@ -30,7 +30,7 @@ DefinitionBlock( Device (PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/jasperlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index 9c220d4538..f95e7aacc3 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -6,7 +6,7 @@ */ #include <baseboard/variants.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h> void mainboard_memory_init_params(FSPM_UPD *memupd) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 865d4ea73c..f030b20cec 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index ff8a4ec661..08c3bde29f 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -8,7 +8,7 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> #include <gpio.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h> static const struct mb_cfg baseboard_memcfg_cfg = { diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index 23db34e66c..388051afa0 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 884199c4c5..cb21c63b0f 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index c996717b0e..ed59af6a96 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include <soc/intel/tigerlake/acpi/platform.asl> + #include <soc/intel/jasperlake/acpi/platform.asl> /* global NVS and variables */ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> @@ -37,7 +37,7 @@ DefinitionBlock( Device (PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/jasperlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c index 8858e44616..f185628df1 100644 --- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c @@ -14,7 +14,7 @@ */ #include <baseboard/variants.h> #include <console/console.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h> #include "board_id.h" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h index 27c645bbde..2fe7631281 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -17,7 +17,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/gpio.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 386936eef8..41921dd46e 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/tigerlake +chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 1915a1e1ff..4de66b3929 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -16,7 +16,7 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> #include <gpio.h> -#include <soc/meminit_jsl.h> +#include <soc/meminit.h> #include <soc/romstage.h> static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = { |