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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2022-07-15 10:24:19 +0800
committerMartin L Roth <gaumless@tutanota.com>2022-07-16 23:16:21 +0000
commita08d5a8086245da92f5ed42fa71ccdb0609a85ce (patch)
tree78dbb606002af2e42e3738e25c7f48e4f7ac00d5 /src/mainboard
parent205e7f676d3e65bf99ca27107cef34ee0a8a4049 (diff)
mb/google/brya/var/osiris: Add wifi sar table
1. Add wifi sar table for osiris 2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG BUG=b:234951991 TEST=build FW and checked SAR table can load by WiFi driver. Cq-Depend: chrome-internal:4871098 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I301dce3229a24dd72b12b84d9eb7606abe10cbba Reviewed-on: https://review.coreboot.org/c/coreboot/+/65869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/brya/Kconfig.name2
-rw-r--r--src/mainboard/google/brya/variants/osiris/variant.c6
2 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 7384a95f7d..1ab85252df 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -228,6 +228,8 @@ config BOARD_GOOGLE_CRAASK
config BOARD_GOOGLE_OSIRIS
bool "-> Osiris"
select BOARD_GOOGLE_BASEBOARD_BRYA
+ select CHROMEOS_WIFI_SAR if CHROMEOS
+ select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
select RT8168_GEN_ACPI_POWER_RESOURCE
select RT8168_GET_MAC_FROM_VPD
select RT8168_SET_LED_MODE
diff --git a/src/mainboard/google/brya/variants/osiris/variant.c b/src/mainboard/google/brya/variants/osiris/variant.c
index e8f7607df0..422a87697d 100644
--- a/src/mainboard/google/brya/variants/osiris/variant.c
+++ b/src/mainboard/google/brya/variants/osiris/variant.c
@@ -3,6 +3,12 @@
#include <baseboard/variants.h>
#include <chip.h>
#include <fw_config.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+ return "wifi_sar_0.hex";
+}
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{