superio/winbond/w83627ehg: Convert romstage to generic component

Convert the serial init to the generic romstage component and
corresponding boards using this sio.

Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5589
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

7 files changed, 13 insertions, 19 deletions

diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index efc4ac7247..1dea57b090 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
@@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	struct sys_info *sysinfo = &sysinfo_car;
 
 	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	enable_rom_decode();
 
@@ -166,11 +167,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		enumerate_ht_chain();
 	}
 
-	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-	enable_rom_decode();
-
 	print_info("now booting... real_main\n");
 
 	if (bist == 0)
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 19f5686d10..abe5f84709 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
@@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	struct sys_info *sysinfo = &sysinfo_car;
 
 	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	enable_rom_decode();
 
@@ -166,13 +167,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		enumerate_ht_chain();
 	}
 
-	// FIXME why is this executed again? --->
-	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-	enable_rom_decode();
-	// <--- FIXME why is this executed again?
-
 	print_info("now booting... real_main\n");
 
 	if (bist == 0)
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 64df82eca1..067d25b233 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -27,11 +27,11 @@
 #include <cpu/x86/lapic.h>
 #include <lib.h>
 #include <cbmem.h>
+#include <superio/winbond/common/winbond.h>
 #include "superio/winbond/w83627ehg/w83627ehg.h"
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c
index f996301088..bf34e9ae51 100644
--- a/src/mainboard/iei/pm-lx-800-r11/romstage.c
+++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c
@@ -32,6 +32,7 @@
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <southbridge/amd/cs5536/early_smbus.c>
 #include <southbridge/amd/cs5536/early_setup.c>
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include <northbridge/amd/lx/raminit.h>
 
@@ -63,7 +64,7 @@ void main(unsigned long bist)
 
 	cs5536_early_setup();
 
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	report_bist_failure(bist);
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 68feb3b403..fd8fbfb2b5 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -37,6 +37,7 @@
 #include <spd.h>
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
@@ -122,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	pnp_enter_ext_func_mode(SERIAL_DEV);
 	/* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
 	pnp_write_config(SERIAL_DEV, 0x24, 0);
-	w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	pnp_exit_ext_func_mode(SERIAL_DEV);
 
 	setup_mb_resource_map();
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 19592f38c9..3048542854 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -37,6 +37,7 @@
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "cpu/x86/bist.h"
 #include <spd.h>
@@ -139,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index ad7dcdec09..3993baeff2 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -39,6 +39,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdfam10/reset_test.c"
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdfam10/debug.c"
@@ -126,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
 	pnp_exit_ext_func_mode(SERIAL_DEV);
 
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */