diff options
author | Furquan Shaikh <furquan@google.com> | 2020-08-10 19:00:07 -0700 |
---|---|---|
committer | Furquan Shaikh <furquan@google.com> | 2020-08-12 04:32:07 +0000 |
commit | 988da3142df49908ca8f344102955a24a540028b (patch) | |
tree | 164a602c9129ad1ba95467439a23573028b8e664 /src/mainboard | |
parent | 45701fd96ea67cb3ee42c2cfd2bb663df4cda588 (diff) |
mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB
This change reorganizes flash map layout for zork to allow WP_RO to
grow to 8MiB. This is to allow more space for the firmware UI screens
in RO. Following changes are made in the layout:
1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for
MRC cache. Next section can start on 64K boundary immediately after
MRC cache.
2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB
each. Each region is currently at ~2MiB of usage.
3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size
supported by coreboot.
4. SMMSTORE is restricted to 4K.
5. RW_LEGACY region is dropped down to ~1.9MiB.
BUG=b:161949925
TEST=Verified that write-protection for RO still works fine, device
boots in recovery and non-recovery mode. Also, verified that the dump
of fmap looks correct:
dump_fmap -h firmware/image-trembyle.serial.bin
name start end size
WP_RO 00800000 01000000 00800000
RO_SECTION 00804000 01000000 007fc000
COREBOOT 00875000 01000000 0078b000
GBB 00805000 00875000 00070000
RO_FRID 00804800 00804840 00000040
FMAP 00804000 00804800 00000800
RO_VPD 00800000 00804000 00004000
RW_LEGACY 0061d000 00800000 001e3000
SMMSTORE 0061c000 0061d000 00001000
RW_NVRAM 00617000 0061c000 00005000
RW_VPD 00615000 00617000 00002000
RW_SHARED 00611000 00615000 00004000
VBLOCK_DEV 00613000 00615000 00002000
SHARED_DATA 00611000 00613000 00002000
RW_ELOG 00610000 00611000 00001000
RW_SECTION_B 00310000 00610000 00300000
RW_FWID_B 0060ff00 00610000 00000100
FW_MAIN_B 00312000 0060ff00 002fdf00
VBLOCK_B 00310000 00312000 00002000
RW_SECTION_A 00010000 00310000 00300000
RW_FWID_A 0030ff00 00310000 00000100
FW_MAIN_A 00012000 0030ff00 002fdf00
VBLOCK_A 00010000 00012000 00002000
RW_MRC_CACHE 00000000 00010000 00010000
SI_BIOS 00000000 01000000 01000000
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/google/zork/chromeos.fmd | 61 |
1 files changed, 30 insertions, 31 deletions
diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index 90cd2d7f90..96db31eed2 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -1,37 +1,36 @@ -FLASH@0xFF000000 0x1000000 { - SI_BIOS@0x0 0x1000000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RW_MRC_CACHE@0x0 0x10000 - MRC_CACHE_HOLE@0x10000 0x11000 +FLASH@0xFF000000 16M { + SI_BIOS@0x0 16M { + # Size is mentioned in decimal instead of 64K because of the + # rules in picasso/Makefile.inc to calculate size of APOB NV. + # Once fmaptool is updated to provide this information, this + # can be changed to be like other entries. + RW_MRC_CACHE@0 65536 + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 } - RW_SECTION_A@0x21000 0x39E000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x38DFC0 - RW_FWID_A@0x39DFC0 0x40 + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 } - RW_SECTION_B@0x3BF000 0x39E000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x38DFC0 - RW_FWID_B@0x39DFC0 0x40 + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K } - RW_ELOG(PRESERVE)@0x75D000 0x4000 - RW_SHARED@0x761000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x765000 0x2000 - RW_NVRAM(PRESERVE)@0x767000 0x5000 - RW_UNUSED@0x76C000 0x14000 - SMMSTORE(PRESERVE)@0x780000 0x20000 - RW_LEGACY(CBFS)@0x7A0000 0x460000 - WP_RO@0xC00000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3FC000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7C0 - GBB@0x1000 0x70000 - COREBOOT(CBFS)@0x71000 0x38B000 + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 4K + RW_LEGACY(CBFS) + WP_RO@8M 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) } } } |