diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-05-13 23:52:30 +1000 |
|---|---|---|
| committer | Idwer Vollering <vidwer@gmail.com> | 2014-05-28 22:53:30 +0200 |
| commit | 92da206532598bd0cec91b2cddc7a1296400d728 (patch) | |
| tree | 67ca596ff788feaf1358375f4415137035cd9ba8 /src/mainboard | |
| parent | b918623f2e754d33226850958abd1a1fdc8c4889 (diff) | |
superio/winbond/w83627uhg: Depreciate romstage component
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.
Convert dependent board to generic winbond serial init. Note the clock
function is actually invalid since it never enters into PNP config mode
to twiddle the register. Further, 48MHz is the default (page 9 of
data-sheet) and so romstage.c need not do anything to the clock rate
hence why it presumably works with this invalid function.
Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5725
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/asrock/imb-a180/romstage.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 5b64cf9c05..8ce496b652 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -35,7 +35,8 @@ #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" #include "cbmem.h" -#include "superio/winbond/w83627uhg/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627uhg/w83627uhg.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) @@ -80,9 +81,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x30); post_code(0x31); - /* Set w83627uhg to 48MHz and enable w83627uhg */ - w83627uhg_set_input_clk_sel(SERIAL_DEV, 0); - w83627uhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } |