mainboard/google/mistral: Add support for Mistral

Adding a new board variant 'Mistral' based on qcs405 soc.

TEST=build

Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

10 files changed, 228 insertions, 0 deletions

diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig
new file mode 100644
index 0000000000..f8e8ac76b0
--- /dev/null
+++ b/src/mainboard/google/mistral/Kconfig
@@ -0,0 +1,43 @@
+
+config BOARD_GOOGLE_MISTRAL_COMMON  # Umbrella option to be selected by variants
+	def_bool n
+
+if BOARD_GOOGLE_MISTRAL_COMMON
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select COMMON_CBFS_SPI_WRAPPER
+	select SOC_QUALCOMM_QCS405
+	select SPI_FLASH
+	select MAINBOARD_HAS_CHROMEOS
+	select MISSING_BOARD_RESET
+
+config VBOOT
+	select VBOOT_VBNV_FLASH
+	select VBOOT_MOCK_SECDATA
+	select VBOOT_NO_BOARD_SUPPORT
+	select GBB_FLAG_FORCE_DEV_SWITCH_ON
+
+config MAINBOARD_DIR
+	string
+	default google/mistral
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+##########################################################
+#### Update below when adding a new derivative board. ####
+##########################################################
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Mistral" if BOARD_GOOGLE_MISTRAL
+
+config GBB_HWID
+	string
+	depends on CHROMEOS
+	default "MISTRAL TEST 1859" if BOARD_GOOGLE_MISTRAL
+
+endif # BOARD_GOOGLE_MISTRAL_COMMON
diff --git a/src/mainboard/google/mistral/Kconfig.name b/src/mainboard/google/mistral/Kconfig.name
new file mode 100644
index 0000000000..ca51fa23e9
--- /dev/null
+++ b/src/mainboard/google/mistral/Kconfig.name
@@ -0,0 +1,4 @@
+
+config BOARD_GOOGLE_MISTRAL
+	bool "Mistral"
+	select BOARD_GOOGLE_MISTRAL_COMMON
diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc
new file mode 100644
index 0000000000..31dc79fff9
--- /dev/null
+++ b/src/mainboard/google/mistral/Makefile.inc
@@ -0,0 +1,14 @@
+
+bootblock-y += memlayout.ld
+bootblock-y += chromeos.c
+bootblock-y += bootblock.c
+
+verstage-y += memlayout.ld
+verstage-y += chromeos.c
+
+romstage-y += memlayout.ld
+romstage-y += chromeos.c
+
+ramstage-y += memlayout.ld
+ramstage-y += chromeos.c
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/mistral/board_info.txt b/src/mainboard/google/mistral/board_info.txt
new file mode 100644
index 0000000000..5ef77d7cb4
--- /dev/null
+++ b/src/mainboard/google/mistral/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Mistral Qualcomm QCS405 reference board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c
new file mode 100644
index 0000000000..6718d52156
--- /dev/null
+++ b/src/mainboard/google/mistral/bootblock.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <timestamp.h>
+
+void bootblock_mainboard_init(void)
+{
+
+}
diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c
new file mode 100644
index 0000000000..538e46fa4b
--- /dev/null
+++ b/src/mainboard/google/mistral/chromeos.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+
+}
diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd
new file mode 100644
index 0000000000..633df2ee42
--- /dev/null
+++ b/src/mainboard/google/mistral/chromeos.fmd
@@ -0,0 +1,51 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License version 2 and
+## only version 2 as published by the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+FLASH@0x0 8M {
+	WP_RO 4M {
+		RO_SECTION 0x204000 {
+			BOOTBLOCK 96K
+			COREBOOT(CBFS)
+			FMAP@0x200000 0x1000
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_VPD 128K
+		RO_DDR_TRAINING(PRESERVE) 8K
+	}
+
+	RW_VPD(PRESERVE) 32K
+	RW_NVRAM(PRESERVE) 16K
+	RW_DDR_TRAINING(PRESERVE) 8K
+	RW_ELOG(PRESERVE) 4K
+	RW_SHARED 4K {
+		SHARED_DATA
+	}
+
+	RW_SECTION_A 1280K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 256
+	}
+
+
+	RW_SECTION_B 1280K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 256
+	}
+
+	RW_LEGACY(CBFS)
+}
diff --git a/src/mainboard/google/mistral/devicetree.cb b/src/mainboard/google/mistral/devicetree.cb
new file mode 100644
index 0000000000..977f4c68d9
--- /dev/null
+++ b/src/mainboard/google/mistral/devicetree.cb
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License version 2 and
+## only version 2 as published by the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip soc/qualcomm/qcs405
+	device cpu_cluster 0 on end
+end
diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c
new file mode 100644
index 0000000000..568d4864a5
--- /dev/null
+++ b/src/mainboard/google/mistral/mainboard.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <bootblock_common.h>
+#include <timestamp.h>
+
+static void mainboard_init(struct device *dev)
+{
+
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.name = CONFIG_MAINBOARD_PART_NUMBER,
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/mistral/memlayout.ld b/src/mainboard/google/mistral/memlayout.ld
new file mode 100644
index 0000000000..cbabf2ee37
--- /dev/null
+++ b/src/mainboard/google/mistral/memlayout.ld
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/memlayout.ld>