mb/intel/shadowmountain: Enable Type-C subsystem

This patch adds the changes to enable the TCSS.

BUG=b:175808146
TEST= Boot shadowmountain board, Test the functionality of the Type-C
ports on both the mainboard and daughterboard by plugging in the Type-C
devices and verified the devices are detected via EC console and in the
OS.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 49 insertions, 2 deletions

diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index 6a5abc160d..2dbd653e0d 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_MAX98373
 	select DRIVERS_INTEL_DPTF
 	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_USB4_RETIMER
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
 	select EC_GOOGLE_CHROMEEC
@@ -19,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_SPD_IN_CBFS
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_CHROMEOS
+	select PCIEXP_HOTPLUG
 	select SOC_INTEL_ALDERLAKE
 
 config CHROMEOS
@@ -54,4 +56,16 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "shadowmountain"
 
+config PCIEXP_HOTPLUG_BUSES
+	int
+	default 42
+
+config PCIEXP_HOTPLUG_MEM
+	hex
+	default 0xc200000  # 194 MiB
+
+config PCIEXP_HOTPLUG_PREFETCH_MEM
+	hex
+	default 0x1c000000 # 448 MiB
+
 endif # BOARD_INTEL_SHADOWMOUNTAIN
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index c0d7864f28..58b931f681 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -12,6 +12,11 @@ chip soc/intel/alderlake
 	register "pmc_gpe0_dw1" = "GPP_D"
 	register "pmc_gpe0_dw2" = "GPP_E"
 
+	# TCSS
+	register "TcssAuxOri" = "1"
+	register "IomTypeCPortPadCfg[0]" = "0x09020005"
+	register "IomTypeCPortPadCfg[1]" = "0x09020006"
+
 	# Enable heci communication
 	register "HeciEnabled" = "1"
 
@@ -193,7 +198,12 @@ chip soc/intel/alderlake
 		device pci 0a.0 off end # Crash-log SRAM
 		device pci 0d.0 on  end # USB xHCI
 		device pci 0d.1 on  end # USB xDCI (OTG)
-		device pci 0d.2 on  end
+		device pci 0d.2 on
+			chip drivers/intel/usb4/retimer
+				register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19)"
+				device generic 0 on end
+			end
+		end
 		device pci 0d.3 on  end # TBT DMA1
 		device pci 0e.0 off end # VMD
 		device pci 10.0 off end
@@ -303,11 +313,34 @@ chip soc/intel/alderlake
 		device pci 1e.3 off end # GSPI1
 		device pci 1f.0 on
 			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
 				device pnp 0c09.0 on end
 			end
 		end # eSPI
 		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 hidden end # PMC
+		device pci 1f.2 hidden
+			# The pmc_mux chip driver is a placeholder for the
+			# PMC.MUX device in the ACPI hierarchy.
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "6"
+						register "usb3_port_number" = "1"
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "4"
+						register "usb3_port_number" = "2"
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end # PMC
 		device pci 1f.3 on  end # Intel Audio SNDW
 		device pci 1f.4 on  end # SMBus
 		device pci 1f.5 on  end # SPI