diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-09-29 18:09:24 +0530 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2020-10-08 19:11:43 +0000 |
| commit | 833b5b33d2fe330873c2412193113bc4ff3fc5f3 (patch) | |
| tree | 4ab635ebedbcb94c7c804095e6c5550237f1fb30 /src/mainboard | |
| parent | 5b3a0ff4f1ac064b3aca61169fbb87a72d4592bd (diff) | |
mb/google/dedede: Configure VR in devicetree
BUG=b:167472333
TEST=Build and boot dedede and observe the slope and offset values
getting updated in the fsp debug log
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I3ea32218040263f0abef9b9dd4c52efb16289fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45825
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1f72eb1432..73b0c61f1b 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -163,6 +163,16 @@ chip soc/intel/jasperlake # register "common_soc_config.<variable_name>" = "value" register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT + # VR config settings + # Imon Slope correction specified in 1/100 increment values. Range is 0-200. + # Eg: 125 = 1.25 + register "ImonSlope" = "100" + + # Imon offset correction. Value is a 2's complement signed integer. + # Units 1/1000, Range 0-63999. + # For an offset = 12.580, use 12580 + register "ImonOffset" = "0" + # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" |