diff options
| author | Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> | 2024-11-19 11:18:37 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-26 05:51:19 +0000 |
| commit | 80caf690d01165e1e395b281b2c14c1057c3598e (patch) | |
| tree | 4022f0a0c8eeb7850b8053a020d6ca702c155461 /src/mainboard | |
| parent | 73a1f02592bd8c8759b97628cfafafd542c31748 (diff) | |
mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W
The RAPL PL1 limit and MMIO PL1 max values should be set as per
silicon TDP as specified in the PDG doc#646929.
BUG=b:378623372
TEST=Build and boot on Trulo board.
Verified PL1 value is updated in DTT and sysfs interfaces.
Output with 15W silicon as below:
cd /sys/class/powercap/
cat intel-rapl/intel-rapl\:0/constraint_0_max_power_uw
15000000
cat intel-rapl/intel-rapl\:0/constraint_0_power_limit_uw
15000000
cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_max_power_uw
15000000
cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_power_limit_uw
15000000
Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85184
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/trulo/overridetree.cb | 26 |
1 files changed, 4 insertions, 22 deletions
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index cbe3840ebf..25aaf80208 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -181,24 +181,6 @@ chip soc/intel/alderlake }, }" - register "power_limits_config[ADL_N_041_6W_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 25, - .tdp_pl4 = 78, - }" - - register "power_limits_config[ADL_N_081_7W_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 25, - .tdp_pl4 = 78, - }" - - register "power_limits_config[ADL_N_081_15W_CORE]" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 35, - .tdp_pl4 = 83, - }" - device domain 0 on device ref igpu on end device ref dtt on @@ -254,8 +236,8 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { - .min_power = 6000, - .max_power = 20000, + .min_power = 5000, + .max_power = 6000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 28 * MSECS_PER_SEC, .granularity = 500 @@ -351,8 +333,8 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { - .min_power = 15000, - .max_power = 20000, + .min_power = 14000, + .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 28 * MSECS_PER_SEC, .granularity = 500 |