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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-05-23 08:42:18 +1000 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-05-23 15:38:35 +0200 |
| commit | 8084e5b6da38865bde976ae02563f83dad37c133 (patch) | |
| tree | 63c8f85b56787ae8e9aeab2168b3f78c9e263553 /src/mainboard | |
| parent | f5037bd570a7cbd2b09fb6d34d3feb77553144f4 (diff) | |
mainboard/google/peppy Fix usage of GNU field designator extension
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.
Change-Id: Idd7305cb34be77894ca4b6062bc0a2dc61126347
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/peppy/romstage.c | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 4e723269ff..38c224b2c0 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -121,32 +121,32 @@ static void copy_spd(struct pei_data *peid) void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { - pei_version: PEI_VERSION, - mchbar: DEFAULT_MCHBAR, - dmibar: DEFAULT_DMIBAR, - epbar: DEFAULT_EPBAR, - pciexbar: DEFAULT_PCIEXBAR, - smbusbar: SMBUS_IO_BASE, - wdbbar: 0x4000000, - wdbsize: 0x1000, - hpet_address: HPET_ADDR, - rcba: DEFAULT_RCBA, - pmbase: DEFAULT_PMBASE, - gpiobase: DEFAULT_GPIOBASE, - temp_mmio_base: 0xfed08000, - system_type: 5, /* ULT */ - tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xff, 0x00, 0xff, 0x00 }, - ec_present: 1, + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 5, /* ULT */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, + .ec_present = 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - dimm_channel0_disabled: 2, - dimm_channel1_disabled: 2, - max_ddr3_freq: 1600, - usb_xhci_on_resume: 1, - usb2_ports: { + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = 1, + .usb2_ports = { /* Length, Enable, OCn#, Location */ { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ USB_PORT_MINI_PCIE }, @@ -165,7 +165,7 @@ void mainboard_romstage_entry(unsigned long bist) { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ USB_PORT_SKIP }, }, - usb3_ports: { + .usb3_ports = { /* Enable, OCn# */ { 1, 0 }, /* P1; Port A, CN6 */ { 0, USB_OC_PIN_SKIP }, /* P2; */ |