diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2023-11-28 16:26:28 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-30 15:03:33 +0000 |
| commit | 722c0b7b210ff31fafd6275e2fa2bd1c0838847c (patch) | |
| tree | b4849463d5ccedc8757b391d4146ceda680bb784 /src/mainboard | |
| parent | fd1c2f488f4ce0e931db3d944ef5fd1faed98fe1 (diff) | |
mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus
interface is per default write-protected in FSP. This avoids that an
SPD-EEPROM on a DRAM module gets overwritten by the host.
On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM
available. Nevertheless, there is a general purpose EEPROM on the same
address available which needs to stay writeable.
This patch disables the default-enabled write protect feature for the
SPD-EEPROM addresses just for mc_ehl1.
Test=Boot into Linux and make sure a write access into the EEPROM is
possible.
Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/romstage_fsp_params.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index 28fca2da10..d386d756a6 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -38,4 +38,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* Enable Row-Hammer prevention */ memupd->FspmConfig.RhPrevention = 1; + if (CONFIG(BOARD_SIEMENS_MC_EHL1)) { + /* Allow writes to EEPROM addresses 0x50..0x57. */ + memupd->FspmConfig.SmbusSpdWriteDisable = 0; + } } |