diff options
| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2019-08-27 16:03:05 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-29 19:47:16 +0000 |
| commit | 71f0ceb03a0f2c68067141a5614ff549b434734e (patch) | |
| tree | 867c2593e09dacc1a9e4ef798314beb3977cb0f4 /src/mainboard | |
| parent | 1cfba67b2c5c84c4bbb131b2f4990a0ee9646cde (diff) | |
mb/google/drallion: Update memory map
This will enable to optionally inject ISH binaries into
coreboot.
BUG:b:139820063
TEST='compile successfully'
Change-Id: I38659460726a3f647cda3bc3efd442f18aea24f0
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/drallion/chromeos.fmd | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index ece0eda099..78b12bd8bd 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -1,27 +1,26 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x400000 { + SI_ALL@0x0 0x402000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 - SI_GBE(PRESERVE)@0x101000 0x2000 - SI_ME@0x103000 0x2f9000 - SI_PDR(PRESERVE)@0x3fc000 0x4000 + SI_ME@0x101000 0x2fd000 + SI_PDR(PRESERVE)@0x3fe000 0x4000 } - SI_BIOS@0x400000 0x1c00000 { - RW_DIAG@0x0 0x12d0000 { - RW_LEGACY(CBFS)@0x0 0x12c0000 - DIAG_NVRAM@0x12c0000 0x10000 + SI_BIOS@0x402000 0x1bfe000 { + RW_DIAG@0x0 0x12ce000 { + RW_LEGACY(CBFS)@0x0 0x12be000 + DIAG_NVRAM@0x12be000 0x10000 } - RW_SECTION_A@0x12d0000 0x280000 { + RW_SECTION_A@0x12ce000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x1550000 0x280000 { + RW_SECTION_B@0x154e000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0x17d0000 0x30000 { + RW_MISC@0x17ce000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -34,7 +33,7 @@ FLASH@0xfe000000 0x2000000 { RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - WP_RO@0x1800000 0x400000 { + WP_RO@0x17fe000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { |