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authorFrank Wu <frank_wu@compal.corp-partner.google.com>2022-10-17 10:29:06 +0800
committerKarthik Ramasubramanian <kramasub@google.com>2022-10-20 16:25:22 +0000
commit6d87ac57e208ee10c7a83551e2d535b230b7a952 (patch)
tree64051da0a5a64be2418981c70c02083ff7a8c20b /src/mainboard
parenta6065ec328de83e8c70cd4b7acd27ad99f882753 (diff)
mb/google/skyrim/var/frostflow: Update GPIO settings
Configure GPIOs based on GPIO_20221014.xlsx of frostflow. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I02272801c85a7c30d24c834a840e026225956fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/skyrim/variants/frostflow/Makefile.inc2
-rw-r--r--src/mainboard/google/skyrim/variants/frostflow/gpio.c22
2 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/variants/frostflow/Makefile.inc b/src/mainboard/google/skyrim/variants/frostflow/Makefile.inc
index 88e75bde52..db72b152a7 100644
--- a/src/mainboard/google/skyrim/variants/frostflow/Makefile.inc
+++ b/src/mainboard/google/skyrim/variants/frostflow/Makefile.inc
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
subdirs-y += ./memory
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/skyrim/variants/frostflow/gpio.c b/src/mainboard/google/skyrim/variants/frostflow/gpio.c
new file mode 100644
index 0000000000..a80693fac6
--- /dev/null
+++ b/src/mainboard/google/skyrim/variants/frostflow/gpio.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* GPIO configuration in ramstage */
+static const struct soc_amd_gpio override_gpio_table[] = {
+ /* EN_PWR_WWAN_X => CAM_PSW_L */
+ PAD_INT(GPIO_8, PULL_NONE, BOTH_EDGES, STATUS_DELIVERY),
+ /* SOC_SAR_INT_L => Unused */
+ PAD_NC(GPIO_17),
+ /* WWAN_RST_L => Unused */
+ PAD_NC(GPIO_42),
+};
+
+void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
+{
+ *size = ARRAY_SIZE(override_gpio_table);
+ *gpio = override_gpio_table;
+}