FUI: Fill in link_m and link_n values

... based on the EDID detailed timing values for
pixel_clock and link_clock.

Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n
respectively.  Other two undocumented registers 0x6f030 and 0x6f034 correspond
to data_m and data_n respectively.

Calculations are based on the intel_link_compute_m_n from linux kernel.

Currently, the value for 0x6f030 does not come up right with our calculations.
Hence, set to hard-coded value.

Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e
Reviewed-on: https://gerrit.chromium.org/gerrit/62915
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4381
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

2 files changed, 38 insertions, 3 deletions

diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 39072186e0..52a7b0b4e8 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -288,6 +288,12 @@ void dp_init_dim_regs(struct intel_dp *dp)
 
 	dp->pfa_sz = (edid->ha << 16) | (edid->va);
 
+	intel_dp_compute_m_n(dp->bpp,
+			     dp->lane_count,
+			     dp->edid.pixel_clock,
+			     dp->edid.link_clock,
+			     &dp->m_n);
+
 	printk(BIOS_SPEW, "dp->stride  = 0x%08x\n",dp->stride);
 	printk(BIOS_SPEW, "dp->htotal  = 0x%08x\n", dp->htotal);
 	printk(BIOS_SPEW, "dp->hblank  = 0x%08x\n", dp->hblank);
@@ -299,6 +305,26 @@ void dp_init_dim_regs(struct intel_dp *dp)
 	printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
 	printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
 	printk(BIOS_SPEW, "dp->pfa_sz  = 0x%08x\n", dp->pfa_sz);
+	printk(BIOS_SPEW, "dp->link_m  = 0x%08x\n", dp->m_n.link_m);
+	printk(BIOS_SPEW, "dp->link_n  = 0x%08x\n", dp->m_n.link_n);
+	printk(BIOS_SPEW, "0x6f030     = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
+	printk(BIOS_SPEW, "0x6f030     = 0x%08x\n", dp->m_n.gmch_m);
+	printk(BIOS_SPEW, "0x6f034     = 0x%08x\n", dp->m_n.gmch_n);
+}
+
+int intel_dp_bw_code_to_link_rate(u8 link_bw);
+
+int intel_dp_bw_code_to_link_rate(u8 link_bw)
+{
+	switch (link_bw) {
+        case DP_LINK_BW_1_62:
+        default:
+		return 162000;
+        case DP_LINK_BW_2_7:
+		return 270000;
+        case DP_LINK_BW_5_4:
+                return 540000;
+	}
 }
 
 int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
@@ -366,6 +392,10 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
 	edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
 	printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
 
+	dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
+
+	printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",dp->edid.pixel_clock, dp->edid.link_clock);
+
 	dp_init_dim_regs(dp);
 
 	/* more undocumented stuff. */
diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c
index 18e0480e13..c1e05472c9 100644
--- a/src/mainboard/google/slippy/i915io.c
+++ b/src/mainboard/google/slippy/i915io.c
@@ -117,9 +117,14 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD");
 
 	/* undocumented. */
 	io_i915_write32(0x7e4a0000,0x6f030);
-	io_i915_write32(0x00800000,0x6f034);
-	io_i915_write32(0x00021000,0x6f040);
-	io_i915_write32(0x00080000,0x6f044);
+	/* io_i915_write32(0x00800000,0x6f034); */
+	/* Write to 0x6f030 has to be 0x7e4ayyyy -- First four hex digits are important.
+	   However, with our formula we always see values 0x7e43yyyy (1366 panel) and
+	   0x7e42yyy (1280 panel) */
+	/* io_i915_write32(TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m,0x6f030); */
+	io_i915_write32(dp->m_n.gmch_n,0x6f034);
+	io_i915_write32(dp->m_n.link_m,0x6f040);
+	io_i915_write32(dp->m_n.link_n,0x6f044);
 
 	/* leave as is for now. */
 	io_i915_write32(dp->htotal,0x6f000);