mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2

Built from a mixture of autoport output, other variants, schematics and
expert guesswork. I don't have this board, but the code has been tested
by someone else and boots successfully (first try) with TianoCore. It's
reasonable to assume most things work, as this board is very similar to
the already-supported variants.

Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61541
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 287 insertions, 5 deletions

diff --git a/src/mainboard/gigabyte/ga-h61m-series/Kconfig b/src/mainboard/gigabyte/ga-h61m-series/Kconfig
index cec2c61d89..8f4366b90d 100644
--- a/src/mainboard/gigabyte/ga-h61m-series/Kconfig
+++ b/src/mainboard/gigabyte/ga-h61m-series/Kconfig
@@ -1,9 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61M_DS2V || BOARD_GIGABYTE_GA_H61MA_D3V
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
+config BOARD_GIGABYTE_GA_H61M_SERIES
+	def_bool n
 	select BOARD_ROMSIZE_KB_4096
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
@@ -18,6 +16,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_OPTION_TABLE
 	select HAVE_CMOS_DEFAULT
 
+if BOARD_GIGABYTE_GA_H61M_SERIES
+
 config MAINBOARD_DIR
 	default "gigabyte/ga-h61m-series"
 
@@ -25,11 +25,13 @@ config VARIANT_DIR
 	default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV
 	default "ga-h61m-ds2v" if BOARD_GIGABYTE_GA_H61M_DS2V
 	default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V
+	default "ga-h61m-ds2"  if BOARD_GIGABYTE_GA_H61M_DS2
 
 config MAINBOARD_PART_NUMBER
 	default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV
 	default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V
 	default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V
+	default "GA-H61M-DS2"  if BOARD_GIGABYTE_GA_H61M_DS2
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@@ -42,4 +44,4 @@ config USBDEBUG_HCD_INDEX # Bottom left port seen from rear
 	int
 	default 2
 
-endif # BOARD_GIGABYTE_GA_H61M*
+endif # BOARD_GIGABYTE_GA_H61M_SERIES
diff --git a/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name
index 15d107d8e5..f584a28cc2 100644
--- a/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name
+++ b/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name
@@ -1,10 +1,17 @@
 config BOARD_GIGABYTE_GA_H61M_S2PV
 	bool "GA-H61M-S2PV"
+	select BOARD_GIGABYTE_GA_H61M_SERIES
+
+config BOARD_GIGABYTE_GA_H61M_DS2
+	bool "GA-H61M-DS2"
+	select BOARD_GIGABYTE_GA_H61M_SERIES
 
 config BOARD_GIGABYTE_GA_H61M_DS2V
 	bool "GA-H61M-DS2V"
+	select BOARD_GIGABYTE_GA_H61M_SERIES
 	select NO_UART_ON_SUPERIO
 
 config BOARD_GIGABYTE_GA_H61MA_D3V
 	bool "GA-H61MA-D3V"
+	select BOARD_GIGABYTE_GA_H61M_SERIES
 	select NO_UART_ON_SUPERIO
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/gpio.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/gpio.c
new file mode 100644
index 0000000000..8c04b38961
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/gpio.c
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio11 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_GPIO,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio47 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio35 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c
new file mode 100644
index 0000000000..659d1b693b
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887 */
+	0x1458a002,	/* Subsystem ID */
+	15,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(2, 0x1458a002),
+	AZALIA_PIN_CFG(2, 0x11, 0x411110f0),
+	AZALIA_PIN_CFG(2, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
+	AZALIA_PIN_CFG(2, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x18, 0x01a19c20),
+	AZALIA_PIN_CFG(2, 0x19, 0x02a19c30),
+	AZALIA_PIN_CFG(2, 0x1a, 0x0181342f),
+	AZALIA_PIN_CFG(2, 0x1b, 0x02214c1f),
+	AZALIA_PIN_CFG(2, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
+	AZALIA_PIN_CFG(2, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(2, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb
new file mode 100644
index 0000000000..3de795488f
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb
@@ -0,0 +1,56 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+
+			register "pcie_port_coalesce" = "true"
+
+			device pci 1c.0 off end	# RP #1
+			device pci 1c.1 on  end	# RP #2: PCIe x1 Port (PCIEX1_1)
+			device pci 1c.2 off end	# RP #3:
+			device pci 1c.3 off end	# RP #4:
+			device pci 1c.4 on  end	# RP #5: Realtek RTL8111F GbE NIC
+			device pci 1c.5 on  end	# RP #6: PCIe x1 Port (PCIEX1_2)
+
+			device pci 1f.0 on	# LPC bridge
+				chip superio/ite/it8728f
+					device pnp 2e.0 off end	# Floppy
+					device pnp 2e.1 on	# COM1
+						io  0x60 = 0x03f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.2 off end	# COM2
+					device pnp 2e.3 off end	# Parallel port
+					device pnp 2e.4 on	# Environment Controller
+						io 0x60 = 0x0a30
+						io 0x62 = 0x0a20
+					end
+					device pnp 2e.5 on	# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+					end
+					device pnp 2e.6 on  end	# Mouse
+					device pnp 2e.7 on	# GPIO
+						irq 0x25 = 0x40
+						irq 0x26 = 0xf7
+						irq 0x27 = 0x10
+						irq 0x2c = 0x80
+						io 0x60  = 0x0000
+						io 0x62  = 0x0a00
+						io 0x64  = 0x0000
+						irq 0x70 = 0x00
+						irq 0x73 = 0x00
+						irq 0xc1 = 0x37
+						irq 0xcb = 0x00
+						irq 0xf0 = 0x10
+						irq 0xf1 = 0x42
+						irq 0xf6 = 0x1c
+					end
+					device pnp 2e.a off end	# CIR
+				end
+			end
+		end
+	end
+end