diff options
| author | Ivy Jian <ivy.jian@quanta.corp-partner.google.com> | 2022-09-05 11:30:48 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-09-08 16:00:04 +0000 |
| commit | 66757b121ab39b168f1059932797f80bc512c35a (patch) | |
| tree | cf10aedfa7cbdad98431beea398cbcae9b44b50e /src/mainboard | |
| parent | d29b4aef1c110a04c1a03b44d5040b5702d02738 (diff) | |
mb/google/rex: Add WWAN poweron sequencing
The PCIe WWAN module used on rex requires control over 4 signals to
successfully power it on. It is desirable to do this before passing
control to the payload, because the modem requires a ~10 seconds
initialization phase before it can be used.
The corrected sequence looks like:
1) Drive device into full reset and enable power in bootblock
2) Deassert FCPO in romstage, after power rails stabilize
3) Deassert WWAN_RST#, then WWAN_PERST# in ramstage
BUG=b:244077118
TEST=FM350 could be enumerated via lspci
Measured signals to check start-up Timing Sequence, tpr/ton1/ton2.
Tpr = 572mS
Ton1 = 6.3s
Ton2 = 6.3+4.17ms
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I6cda9348ef7f54efe5ba2358040596a1c2da1b13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67332
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/gpio.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 23a0f5b52a..52186bc607 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -105,7 +105,7 @@ static const struct pad_config gpio_table_id0[] = { /* GPP_C04 : [] ==> EN_WCAM_PWR */ PAD_CFG_GPO_LOCK(GPP_C04, 0, LOCK_CONFIG), /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */ - PAD_CFG_GPO(GPP_C05, 0, PLTRST), + PAD_CFG_GPO(GPP_C05, 1, PLTRST), /* GPP_C06 : [] ==> USI_REPORT_EN */ PAD_CFG_GPO(GPP_C06, 0, DEEP), /* GPP_C07 : [] ==> USI_INT */ @@ -370,14 +370,21 @@ static const struct pad_config gpio_table_id0[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table_id0[] = { + /* GPP_B17 : [] ==> EN_WWAN_PWR */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), - + /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP (updated in ramstage) */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), + /* GPP_A15 : [] ==> WWAN_RST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), + /* GPP_E07 : [] ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ @@ -414,6 +421,8 @@ static const struct pad_config default_early_gpio_table[] = { static const struct pad_config romstage_gpio_table_id0[] = { /* A20 : [] ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_A20, 0, DEEP), + /* GPP_E07 : [] ==> WWAN_FCPO_L */ + PAD_CFG_GPO(GPP_E07, 1, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) |