diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-04-26 14:03:32 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-16 13:23:05 +0000 |
| commit | 6438084eab6cfe3047fe64966e2b473aa96529de (patch) | |
| tree | 97d4b5856b8402dfc7ae4be4ee4420b455dac64b /src/mainboard | |
| parent | eda66c313b5c5491738a0a5e884caba14c07731f (diff) | |
mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetree
This mainboard uses all three internal Ethernet GbE-TSN controllers. Two
of them are initialized by the Programmable Services Engine (PSE).
This patch enables the Serial Gigabit Media Independent Interface
(SGMII) mode for GbE PSE0 and GbE PSE1. By setting PCH PSE DMA pins to
host owned, the IO is under control of the IA processor cores through
system software.
TEST:
- Boot mc_ehl2 into Linux and check inet addr via 'ip a'
Change-Id: I74e660548b2c44d5dbdb6023d5a36cfdd7e96f43
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index ffcf1da9fe..72e4b0f2da 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -103,6 +103,10 @@ chip soc/intel/elkhartlake # TSN GBE related UPDs register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" register "PchTsnGbeSgmiiEnable" = "1" + register "PseTsnGbeSgmiiEnable[0]" = "1" + register "PseTsnGbeSgmiiEnable[1]" = "1" + register "PseDmaOwn[0]" = "Host_Owned" + register "PseDmaOwn[1]" = "Host_Owned" register "common_soc_config" = "{ .i2c[2] = { |