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authorMaxim Polyakov <max.senia.poliak@gmail.com>2021-05-16 17:43:00 +0300
committerFelix Held <felix-coreboot@felixheld.de>2021-09-07 14:21:03 +0000
commit5e3854ae7b585d798974eb649ca9e6088b54debf (patch)
treef0cbcbfa05f17c0f3a5c609495fa0a6251ef18a3 /src/mainboard
parent8e1a767c9c06e28a1bb7c2a4d8590cbb32929e9e (diff)
kontron/mal10: Set up GPIOs in CPLD/EC
The COMe module connector implements 8 GPIO lines from the CPLD/EC pins. Use the Kempld GPIO driver[1] to configure these pins in accordance with the COM Express Module Base Specification [2]. TEST = Set different logic states for the pin configured as outputs and check them with an oscilloscope. [1] CB:47595 , Change-Id: Id767aa451fbf2ca1c0dccfc9aa2c024c6f37c1bb [2] page 79-81, PICMG (R) COM.0 Revision 3.0 COM Express (R) Base Specification - March 31, 2017. Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54380 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/kontron/mal10/variants/mal10/devicetree.cb11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb
index 1421cb7905..5c89a644d9 100644
--- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb
+++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb
@@ -74,6 +74,17 @@ chip soc/intel/apollolake
device generic 1.0 on # I2C
register "i2c_frequency" = "KEMPLD_I2C_FREQ_FAST_MODE_400KHZ"
end
+ device gpio 0 on # GPIO
+ # The connector implements 8 GPIO lines only
+ register "gpio[0]" = "KEMPLD_GPIO_INPUT"
+ register "gpio[1]" = "KEMPLD_GPIO_INPUT"
+ register "gpio[2]" = "KEMPLD_GPIO_INPUT"
+ register "gpio[3]" = "KEMPLD_GPIO_INPUT"
+ register "gpio[4]" = "KEMPLD_GPIO_OUTPUT_LOW"
+ register "gpio[5]" = "KEMPLD_GPIO_OUTPUT_LOW"
+ register "gpio[6]" = "KEMPLD_GPIO_OUTPUT_LOW"
+ register "gpio[7]" = "KEMPLD_GPIO_OUTPUT_LOW"
+ end
end
end # LPC
device pci 1f.1 on # SMBUS