diff options
| author | David Hendricks <dhendrix@chromium.org> | 2013-02-10 15:50:20 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-02-11 02:31:34 +0100 |
| commit | 5d994634a268d29b61c98f40f4793334078509c4 (patch) | |
| tree | 16888af3c0249188b82947d62a68e81a1c27abf2 /src/mainboard | |
| parent | a40435af84c5cd2175b842ff0cbd9d1e909c2ce6 (diff) | |
armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply
the same way on ARM platforms. On x86 they refer to the low memory
region where coreboot tables reside.
However on ARM we don't have such a region which is architecturally
defined. So instead we'll use the CPU-defined DRAM base address and
the mainboard-defined DRAM size.
This also has the pleasant side-effect of fixing the coreboot tables
to not clobber ramstage code...
Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2351
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/snow/ramstage.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index d280dbe050..b779999c51 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -30,9 +30,11 @@ void main(void) printk(BIOS_INFO, "hello from ramstage\n"); #if CONFIG_WRITE_HIGH_TABLES - /* Leave some space for ACPI tables */ - high_tables_base = CONFIG_RAMBASE; - high_tables_size = CONFIG_RAMBASE + 0x100000; + /* place at top of physical memory */ + high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; + high_tables_base = CONFIG_SYS_SDRAM_BASE + + ((CONFIG_DRAM_SIZE_MB * 1024) * CONFIG_NR_DRAM_BANKS) - + CONFIG_COREBOOT_TABLES_SIZE; #endif hardwaremain(0); |