diff options
| author | Tarun Tuli <taruntuli@google.com> | 2023-03-29 13:18:43 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-03 13:23:56 +0000 |
| commit | 537213a40ece548857c18e3529b0c31ad63aafff (patch) | |
| tree | 3cc2b07bea9979682d784d734e4bc0d0dac31182 /src/mainboard | |
| parent | 8605cf5fe944193231349dc73199935e25915694 (diff) | |
mb/google/brya/variants/hades: Add CPU power limits
Add CPU power limits support and values for RPL on Hades
BUG=b:269371363
TEST=builds
Change-Id: I22ef56152abe5a23067c5e923b07d60dc9fac8e7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73895
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
4 files changed, 68 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc index fd45b948ff..7c75e20e41 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc @@ -1 +1,2 @@ romstage-y += memory.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c new file mode 100644 index 0000000000..4858eb70bd --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> + +#include <drivers/intel/dptf/chip.h> +#include <intelblocks/power_limit.h> + +WEAK_DEV_PTR(dptf_policy); + +void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) +{ + if (!num_entries) + return; + + const struct device *policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = policy_dev->chip_info; + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + u8 tdp = get_cpu_tdp(); + + for (size_t i = 0; i < num_entries; i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + struct dptf_power_limits *settings = &config->controls.power_limits; + config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config = conf->power_limits_config; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + MILLIWATTS_TO_WATTS); + printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power, + limits[i].pl4_power); + } + } +} diff --git a/src/mainboard/google/brya/variants/hades/Makefile.inc b/src/mainboard/google/brya/variants/hades/Makefile.inc index 2fa692abed..837101ea25 100644 --- a/src/mainboard/google/brya/variants/hades/Makefile.inc +++ b/src/mainboard/google/brya/variants/hades/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/hades/ramstage.c b/src/mainboard/google/brya/variants/hades/ramstage.c new file mode 100644 index 0000000000..e42b8ea098 --- /dev/null +++ b/src/mainboard/google/brya/variants/hades/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* Following values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} |