diff options
| author | Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> | 2017-06-21 16:42:53 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-27 20:46:48 +0000 |
| commit | 4692e2fc95605a997cd9cd1cdb711e6c1f6869bc (patch) | |
| tree | 497ecf92fcd4f33d4e6686f374a8d19754cf3805 /src/mainboard | |
| parent | b3f2c9ac5977ec4d4a0391a202f90a923d06895c (diff) | |
mainboard/google/soraka: Update VR config settings
Update Psi2Threshold, IccMax, AcLoadline, DcLoadline
VR config settings as per board design.
BUG=b:62063434
BRANCH=none
TEST=Build and boot soraka.
Change-Id: I254bbb88b82ddf278f0ec71bc98873df1d5e0d27
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: G Naveen <naveen.g@intel.com>
Reviewed-on: https://review.coreboot.org/20309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/devicetree.cb | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 2785131f43..58287fa4ec 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -72,65 +72,75 @@ chip soc/intel/skylake #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi2Threshold | 2A | 2A | 2A | 2A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | + #| IccMax | 5A | 24A | 24A | 24A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | + #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), + .icc_max = VR_CFG_AMP(5), .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, }" register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, + .ac_loadline = 550, + .dc_loadline = 420, }" register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, + .ac_loadline = 550, + .dc_loadline = 420, }" # Enable Root port 1. |