Eliminate special case id.inc/id.lds in favor of a configuration variable ID_SECTION_OFFSET

which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative)
where necessary (if romstraps get in the way).
For Kconfig, the special case is set per southbridge (as these define the necessity for this
workaround), for newconfig it's added to each single board.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

44 files changed, 115 insertions, 54 deletions

diff --git a/src/mainboard/Makefile.k8_ck804.inc b/src/mainboard/Makefile.k8_ck804.inc
index e412f8e3fb..ad394fc7c9 100644
--- a/src/mainboard/Makefile.k8_ck804.inc
+++ b/src/mainboard/Makefile.k8_ck804.inc
@@ -39,7 +39,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/ck804/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/ck804/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -47,7 +47,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/ck804/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/ck804/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
index 35e0965fba..5a17e3449c 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
@@ -113,6 +113,8 @@ uses CONFIG_AMDMCT
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_AMD_UCODE_PATCH_FILE
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -357,5 +359,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb
index b49951400f..374629c5b3 100644
--- a/src/mainboard/asus/a8n_e/Config.lb
+++ b/src/mainboard/asus/a8n_e/Config.lb
@@ -78,8 +78,8 @@ else
 	end
 end
 # Include an ID string (for safe flashing).
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 # ROMSTRAP table for CK804.
 if CONFIG_HAVE_FAILOVER_BOOT
 	if CONFIG_USE_FAILOVER_IMAGE
diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb
index 02d4407739..a03db4bb0b 100644
--- a/src/mainboard/asus/a8n_e/Options.lb
+++ b/src/mainboard/asus/a8n_e/Options.lb
@@ -94,6 +94,7 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_ID_SECTION_OFFSET
 
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE
@@ -162,5 +163,6 @@ default CONFIG_TTYS0_LCS = 0x3
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_ID_SECTION_OFFSET = 0x80
 
 end
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
index 40a96f4ce1..6cca586272 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
@@ -113,8 +113,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/sis/sis966/id.inc
-ldscript /southbridge/sis/sis966/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc b/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc
index 1130d0711b..35c46f05a2 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc
@@ -33,14 +33,14 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/sis/sis966/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/sis/sis966/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
 
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
index 97a8a4ccc2..252d5880e6 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
@@ -115,6 +115,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -347,5 +349,6 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
 ### End Options.lb
 end
diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb
index cabb1b29f9..c84d73c724 100644
--- a/src/mainboard/gigabyte/m57sli/Config.lb
+++ b/src/mainboard/gigabyte/m57sli/Config.lb
@@ -111,8 +111,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/gigabyte/m57sli/Makefile.inc b/src/mainboard/gigabyte/m57sli/Makefile.inc
index 12d966ca38..44fedbb1b9 100644
--- a/src/mainboard/gigabyte/m57sli/Makefile.inc
+++ b/src/mainboard/gigabyte/m57sli/Makefile.inc
@@ -36,7 +36,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -44,7 +44,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
diff --git a/src/mainboard/gigabyte/m57sli/Options.lb b/src/mainboard/gigabyte/m57sli/Options.lb
index df828f77f8..3010a2ad68 100644
--- a/src/mainboard/gigabyte/m57sli/Options.lb
+++ b/src/mainboard/gigabyte/m57sli/Options.lb
@@ -116,6 +116,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
 uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
+
+uses CONFIG_ID_SECTION_OFFSET
 ###
 ### Build options
 ###
@@ -356,5 +358,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb
index ce8565cd87..adc58a9a11 100644
--- a/src/mainboard/msi/ms7135/Config.lb
+++ b/src/mainboard/msi/ms7135/Config.lb
@@ -107,8 +107,8 @@ end
 ##
 ## Include an ID string (for safe flashing).
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
diff --git a/src/mainboard/msi/ms7135/Options.lb b/src/mainboard/msi/ms7135/Options.lb
index 23377342d0..b3b2b4beaf 100644
--- a/src/mainboard/msi/ms7135/Options.lb
+++ b/src/mainboard/msi/ms7135/Options.lb
@@ -99,6 +99,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ## ---> 512 Kbytes 
 default CONFIG_ROM_SIZE=(512*1024)
@@ -313,5 +315,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb
index b4600611fd..f420731f42 100644
--- a/src/mainboard/msi/ms7260/Config.lb
+++ b/src/mainboard/msi/ms7260/Config.lb
@@ -93,8 +93,8 @@ else
   end
 end
 
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 # ROMSTRAP table for MCP55.
 if CONFIG_HAVE_FAILOVER_BOOT
diff --git a/src/mainboard/msi/ms7260/Makefile.inc b/src/mainboard/msi/ms7260/Makefile.inc
index f10f36c128..2baa947895 100644
--- a/src/mainboard/msi/ms7260/Makefile.inc
+++ b/src/mainboard/msi/ms7260/Makefile.inc
@@ -33,14 +33,14 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
 
diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb
index 54b62c1d01..1be372ae6c 100644
--- a/src/mainboard/msi/ms7260/Options.lb
+++ b/src/mainboard/msi/ms7260/Options.lb
@@ -96,6 +96,7 @@ uses CONFIG_AP_CODE_IN_CAR
 uses CONFIG_MEM_TRAIN_SEQ
 uses CONFIG_WAIT_BEFORE_CPUS_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_ID_SECTION_OFFSET
 
 default CONFIG_ROM_SIZE = 512 * 1024
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
@@ -182,5 +183,6 @@ default CONFIG_TTYS0_LCS = 0x3
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_ID_SECTION_OFFSET=0x80
 
 end
diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb
index 8faf6117f4..ec1211e7b4 100644
--- a/src/mainboard/msi/ms9282/Config.lb
+++ b/src/mainboard/msi/ms9282/Config.lb
@@ -94,8 +94,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/msi/ms9282/Makefile.inc b/src/mainboard/msi/ms9282/Makefile.inc
index 510ee6f046..d04e6f5731 100644
--- a/src/mainboard/msi/ms9282/Makefile.inc
+++ b/src/mainboard/msi/ms9282/Makefile.inc
@@ -35,14 +35,14 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
 
diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb
index 146cc217e0..ee8be01679 100644
--- a/src/mainboard/msi/ms9282/Options.lb
+++ b/src/mainboard/msi/ms9282/Options.lb
@@ -99,6 +99,8 @@ uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes
 default CONFIG_ROM_SIZE=524288
@@ -303,5 +305,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb
index 0b1bfb0ac1..ba30037815 100644
--- a/src/mainboard/nvidia/l1_2pvv/Config.lb
+++ b/src/mainboard/nvidia/l1_2pvv/Config.lb
@@ -141,8 +141,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/nvidia/l1_2pvv/Makefile.inc b/src/mainboard/nvidia/l1_2pvv/Makefile.inc
index 66cc3e6cb0..ccb1094a0e 100644
--- a/src/mainboard/nvidia/l1_2pvv/Makefile.inc
+++ b/src/mainboard/nvidia/l1_2pvv/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb
index b7b445af36..00efb92b09 100644
--- a/src/mainboard/nvidia/l1_2pvv/Options.lb
+++ b/src/mainboard/nvidia/l1_2pvv/Options.lb
@@ -113,6 +113,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -345,5 +347,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb
index b00c2bc331..2781be8d77 100644
--- a/src/mainboard/sunw/ultra40/Config.lb
+++ b/src/mainboard/sunw/ultra40/Config.lb
@@ -62,8 +62,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
diff --git a/src/mainboard/sunw/ultra40/Options.lb b/src/mainboard/sunw/ultra40/Options.lb
index c9d550ed8d..e820fd03f8 100644
--- a/src/mainboard/sunw/ultra40/Options.lb
+++ b/src/mainboard/sunw/ultra40/Options.lb
@@ -69,6 +69,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes 
 #default CONFIG_ROM_SIZE=524288
@@ -272,5 +274,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/supermicro/h8dme/Config.lb b/src/mainboard/supermicro/h8dme/Config.lb
index 2141907900..18cde515db 100644
--- a/src/mainboard/supermicro/h8dme/Config.lb
+++ b/src/mainboard/supermicro/h8dme/Config.lb
@@ -108,8 +108,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/supermicro/h8dme/Makefile.inc b/src/mainboard/supermicro/h8dme/Makefile.inc
index 8075ba2a34..d53db014ed 100644
--- a/src/mainboard/supermicro/h8dme/Makefile.inc
+++ b/src/mainboard/supermicro/h8dme/Makefile.inc
@@ -34,7 +34,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -42,7 +42,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
diff --git a/src/mainboard/supermicro/h8dme/Options.lb b/src/mainboard/supermicro/h8dme/Options.lb
index 5a361350bc..85d8331701 100644
--- a/src/mainboard/supermicro/h8dme/Options.lb
+++ b/src/mainboard/supermicro/h8dme/Options.lb
@@ -114,6 +114,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -347,5 +349,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb
index cc95167ddf..13db09a54d 100644
--- a/src/mainboard/supermicro/h8dmr/Config.lb
+++ b/src/mainboard/supermicro/h8dmr/Config.lb
@@ -110,8 +110,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/supermicro/h8dmr/Makefile.inc b/src/mainboard/supermicro/h8dmr/Makefile.inc
index 8b64208a18..5d5c44ae4b 100644
--- a/src/mainboard/supermicro/h8dmr/Makefile.inc
+++ b/src/mainboard/supermicro/h8dmr/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
diff --git a/src/mainboard/supermicro/h8dmr/Options.lb b/src/mainboard/supermicro/h8dmr/Options.lb
index 5e457d03aa..f0e9082663 100644
--- a/src/mainboard/supermicro/h8dmr/Options.lb
+++ b/src/mainboard/supermicro/h8dmr/Options.lb
@@ -112,6 +112,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -345,5 +347,7 @@ default CONFIG_USE_FAILOVER_IMAGE=0
 default CONFIG_USE_FALLBACK_IMAGE=0
 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Config.lb b/src/mainboard/supermicro/h8dmr_fam10/Config.lb
index cd9dd541e2..fe2d1b6ff8 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/Config.lb
+++ b/src/mainboard/supermicro/h8dmr_fam10/Config.lb
@@ -112,8 +112,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc b/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
index 8b64208a18..5d5c44ae4b 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
+++ b/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Options.lb b/src/mainboard/supermicro/h8dmr_fam10/Options.lb
index e2739a6fba..a7d3ca8095 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/Options.lb
+++ b/src/mainboard/supermicro/h8dmr_fam10/Options.lb
@@ -115,6 +115,7 @@ uses CONFIG_AMDMCT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_AMD_UCODE_PATCH_FILE
+uses CONFIG_ID_SECTION_OFFSET
 
 ###
 ### Build options
@@ -356,5 +357,7 @@ default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 default CONFIG_USE_FAILOVER_IMAGE=0
 default CONFIG_USE_FALLBACK_IMAGE=0
 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
+
+default CONFIG_ID_SECTION_OFFSET=0x80
 ### End Options.lb
 end
diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb
index 53da12bcaf..42627a35f1 100644
--- a/src/mainboard/tyan/s2891/Config.lb
+++ b/src/mainboard/tyan/s2891/Config.lb
@@ -77,8 +77,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb
index 63c5f935da..a0ed35b74c 100644
--- a/src/mainboard/tyan/s2891/Options.lb
+++ b/src/mainboard/tyan/s2891/Options.lb
@@ -77,6 +77,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=512*1024
 
@@ -294,5 +296,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb
index 35328e5446..38645588c7 100644
--- a/src/mainboard/tyan/s2892/Config.lb
+++ b/src/mainboard/tyan/s2892/Config.lb
@@ -78,8 +78,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb
index 89a897bf96..e3f1606cf3 100644
--- a/src/mainboard/tyan/s2892/Options.lb
+++ b/src/mainboard/tyan/s2892/Options.lb
@@ -71,6 +71,8 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE
 uses CONFIG_SB_HT_CHAIN_ON_BUS0
 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=1024*1024
 
@@ -282,5 +284,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb
index e4946de971..1b7f808b40 100644
--- a/src/mainboard/tyan/s2895/Config.lb
+++ b/src/mainboard/tyan/s2895/Config.lb
@@ -90,8 +90,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/ck804/id.inc
-ldscript /southbridge/nvidia/ck804/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for CK804
diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb
index 864fc30dc3..6659c9ad38 100644
--- a/src/mainboard/tyan/s2895/Options.lb
+++ b/src/mainboard/tyan/s2895/Options.lb
@@ -82,6 +82,8 @@ uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
 uses CONFIG_RAMTOP
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE=1024*1024
 
@@ -303,5 +305,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb
index 08f824b347..35511f83ca 100644
--- a/src/mainboard/tyan/s2912/Config.lb
+++ b/src/mainboard/tyan/s2912/Config.lb
@@ -111,8 +111,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/tyan/s2912/Makefile.inc b/src/mainboard/tyan/s2912/Makefile.inc
index acfa14f2e4..c21cdb3574 100644
--- a/src/mainboard/tyan/s2912/Makefile.inc
+++ b/src/mainboard/tyan/s2912/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
diff --git a/src/mainboard/tyan/s2912/Options.lb b/src/mainboard/tyan/s2912/Options.lb
index a8de386fef..52d8202437 100644
--- a/src/mainboard/tyan/s2912/Options.lb
+++ b/src/mainboard/tyan/s2912/Options.lb
@@ -113,6 +113,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
+uses CONFIG_ID_SECTION_OFFSET
+
 ###
 ### Build options
 ###
@@ -347,5 +349,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end
diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb
index f3765f27f7..538ababb8f 100644
--- a/src/mainboard/tyan/s2912_fam10/Config.lb
+++ b/src/mainboard/tyan/s2912_fam10/Config.lb
@@ -111,8 +111,8 @@ end
 ##
 ## Include an id string (For safe flashing)
 ##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
 
 ##
 ## ROMSTRAP table for MCP55
diff --git a/src/mainboard/tyan/s2912_fam10/Makefile.inc b/src/mainboard/tyan/s2912_fam10/Makefile.inc
index acfa14f2e4..c21cdb3574 100644
--- a/src/mainboard/tyan/s2912_fam10/Makefile.inc
+++ b/src/mainboard/tyan/s2912_fam10/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb
index 0a73728ef5..d9444d810a 100644
--- a/src/mainboard/tyan/s2912_fam10/Options.lb
+++ b/src/mainboard/tyan/s2912_fam10/Options.lb
@@ -115,6 +115,7 @@ uses CONFIG_AMDMCT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_AMD_UCODE_PATCH_FILE
+uses CONFIG_ID_SECTION_OFFSET
 
 ###
 ### Build options
@@ -355,5 +356,7 @@ default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+default CONFIG_ID_SECTION_OFFSET=0x80
+
 ### End Options.lb
 end