diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-02-20 20:18:10 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-02-25 03:56:52 +0000 |
| commit | 313fdb28ca6b6479c3305d8a385389de0b2290dd (patch) | |
| tree | f4596187d230fecbaf825315f76c4d2bfaa3bbe8 /src/mainboard | |
| parent | 4bbace87aa6c239cbfea7703daaa0135467109cc (diff) | |
mb/google/rex/var/ovis: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/ovis using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: I891b5a6d2c29f5d940793a4e90215265f2a4fcd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rex/variants/ovis/gpio.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/mainboard/google/rex/variants/ovis/gpio.c b/src/mainboard/google/rex/variants/ovis/gpio.c index 69c5c05c7a..f188929102 100644 --- a/src/mainboard/google/rex/variants/ovis/gpio.c +++ b/src/mainboard/google/rex/variants/ovis/gpio.c @@ -45,10 +45,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_IRQ_WAKE(GPP_A17, NONE, PLTRST, LEVEL, INVERT), /* GPP_A18 : [] ==> CAM_PSW_L */ PAD_NC(GPP_A18, NONE), - /* GPP_A19 : [] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_A19, 1, DEEP), - /* GPP_A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG), /* GPP_A21 : [] ==> WWAN_CONFIG2 */ PAD_NC(GPP_A21, NONE), @@ -377,6 +373,9 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + /* GPP_B18 : [] ==> I2C4_SDA */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), /* GPP_B19 : [] ==> I2C4_SCL */ @@ -395,9 +394,6 @@ static const struct pad_config early_gpio_table[] = { /* GPP_E13 : [] ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* GPP_A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_A20, 0, DEEP), - /* GPP_C13 : [] ==> LAN_PERST_L */ PAD_CFG_GPO(GPP_C13, 0, DEEP), @@ -406,15 +402,18 @@ static const struct pad_config early_gpio_table[] = { /* GPP_D02 : [] ==> SD_PERST_L */ PAD_CFG_GPO(GPP_D02, 0, DEEP), + + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), }; static const struct pad_config romstage_gpio_table[] = { /* GPP_C13 : [] ==> LAN_PERST_L */ PAD_CFG_GPO(GPP_C13, 0, DEEP), - /* A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_A20, 0, DEEP), /* GPP_D02 : [] ==> SD_PERST_L */ PAD_CFG_GPO(GPP_D02, 0, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) |