mb/amd/bettong: Drop unmaintained ROMCC board

Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: I1bce09ba5041a6636f900de611846467653f35a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

24 files changed, 0 insertions, 1942 deletions

diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
deleted file mode 100644
index 22a8403119..0000000000
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci_def.h>
-#include <device/device.h>
-#include <AGESA.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <northbridge/amd/pi/00660F01/chip.h>
-#include <FchPlatform.h>
-#include <stdlib.h>
-#include <string.h>
-#include <northbridge/amd/pi/dimmSpd.h>
-#include <boardid.h>
-
-#include "imc.h"
-#include "hudson.h"
-
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
-static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_READ_SPD,                 board_ReadSpd },
-	{AGESA_DO_RESET,                 agesa_Reset },
-	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config },
-	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-static const GPIO_CONTROL oem_bettong_gpio[] = {
-	{86, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA},
-	{64, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA},
-	{-1}
-};
-
-/* Bettong Hardware Monitor Fan Control
- * Hardware limitation:
- *  HWM will fail to read the input temperature via I2C if other
- *  software switches the I2C address.  AMD recommends using IMC
- *  to control fans, instead of HWM.
- */
-static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
-{
-	/* Enable IMC fan control. the recommand way */
-	imc_reg_init();
-
-	FchParams->Imc.ImcEnable = TRUE;
-	FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
-	FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
-
-	memset(&FchParams->Imc.EcStruct, 0, sizeof(FCH_EC));
-}
-
-/**
- * Fch Oem setting callback
- *
- *  Configure platform specific Hudson device,
- *   such as Azalia, SATA, IMC etc.
- */
-AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
-{
-	AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
-
-	if (StdHeader->Func == AMD_INIT_RESET) {
-		FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
-
-		FchParams_reset->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams_reset->FchReset.Xhci1Enable = FALSE;
-		FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio;
-	} else if (StdHeader->Func == AMD_INIT_ENV) {
-		FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-
-		if (CONFIG(HUDSON_IMC_FWM))
-			oem_fan_control(FchParams_env);
-
-		/* XHCI configuration */
-		if (CONFIG(HUDSON_XHCI_ENABLE))
-			FchParams_env->Usb.Xhci0Enable = TRUE;
-		else
-			FchParams_env->Usb.Xhci0Enable = FALSE;
-
-		FchParams_env->Usb.Xhci1Enable = FALSE;
-		FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is irremovable. */
-
-		/* sata configuration */
-		/* SD configuration */
-		/* Rev F has an on-board eMMC, which only supports SD 2.0 */
-		if (board_id() == 'F') {
-			FchParams_env->Sd.SdConfig = SdVer2;
-		}
-	}
-	printk(BIOS_DEBUG, "Done\n");
-
-	return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
-	int spdAddress;
-
-	if (!ENV_ROMSTAGE)
-		return AGESA_UNSUPPORTED;
-
-	DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
-
-	if (dev == NULL)
-		return AGESA_ERROR;
-
-	DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
-
-	if (config == NULL)
-		return AGESA_ERROR;
-
-	UINT8 spdAddrLookup_rev_F [2][2][4]= {
-		{ {0xA0, 0xA2}, {0xA4, 0xAC}, }, /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */
-		{ {0x00, 0x00}, {0x00, 0x00}, }, /* socket 1 - Channel 0 & 1 - 8-bit SPD addresses */
-	};
-
-	if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
-		return AGESA_ERROR;
-	if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
-		return AGESA_ERROR;
-	if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
-		return AGESA_ERROR;
-	if (board_id() == 'F')
-		spdAddress = spdAddrLookup_rev_F
-			[info->SocketId] [info->MemChannelId] [info->DimmId];
-	else
-		spdAddress = config->spdAddrLookup
-			[info->SocketId] [info->MemChannelId] [info->DimmId];
-
-	if (spdAddress == 0)
-		return AGESA_ERROR;
-	int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
-	if (err)
-		return AGESA_ERROR;
-
-	return AGESA_SUCCESS;
-}
diff --git a/src/mainboard/amd/bettong/BiosCallOuts.h b/src/mainboard/amd/bettong/BiosCallOuts.h
deleted file mode 100644
index 8c2a047099..0000000000
--- a/src/mainboard/amd/bettong/BiosCallOuts.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define FAN_INPUT_INTERNAL_DIODE	0
-#define FAN_INPUT_TEMP0			1
-#define FAN_INPUT_TEMP1			2
-#define FAN_INPUT_TEMP2			3
-#define FAN_INPUT_TEMP3			4
-#define FAN_INPUT_TEMP0_FILTER		5
-#define FAN_INPUT_ZERO			6
-#define FAN_INPUT_DISABLED		7
-
-#define FAN_AUTOMODE			(1 << 0)
-#define FAN_LINEARMODE			(1 << 1)
-#define FAN_STEPMODE			~(1 << 1)
-#define FAN_POLARITY_HIGH		(1 << 2)
-#define FAN_POLARITY_LOW		~(1 << 2)
-
-/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
-#define FREQ_28KHZ			0x0
-#define FREQ_25KHZ			0x1
-#define FREQ_23KHZ			0x2
-#define FREQ_21KHZ			0x3
-#define FREQ_29KHZ			0x4
-#define FREQ_18KHZ			0x5
-#define FREQ_100HZ			0xF7
-#define FREQ_87HZ			0xF8
-#define FREQ_58HZ			0xF9
-#define FREQ_44HZ			0xFA
-#define FREQ_35HZ			0xFB
-#define FREQ_29HZ			0xFC
-#define FREQ_22HZ			0xFD
-#define FREQ_14HZ			0xFE
-#define FREQ_11HZ			0xFF
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
deleted file mode 100644
index 4617360ea1..0000000000
--- a/src/mainboard/amd/bettong/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-config BOARD_AMD_BETTONG
-	def_bool n
-
-if BOARD_AMD_BETTONG
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	#select BINARYPI_LEGACY_WRAPPER
-	#select ROMCC_BOOTBLOCK
-	select CPU_AMD_PI_00660F01
-	select NORTHBRIDGE_AMD_PI_00660F01
-	select SOUTHBRIDGE_AMD_PI_KERN
-	select DEFAULT_POST_ON_LPC
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_8192
-	select GFXUMA
-
-config MAINBOARD_DIR
-	string
-	default "amd/bettong"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "FP4"
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config HUDSON_LEGACY_FREE
-	bool
-	default y
-
-endif # BOARD_AMD_BETTONG
diff --git a/src/mainboard/amd/bettong/Kconfig.name b/src/mainboard/amd/bettong/Kconfig.name
deleted file mode 100644
index 4bd13291cd..0000000000
--- a/src/mainboard/amd/bettong/Kconfig.name
+++ /dev/null
@@ -1,3 +0,0 @@
-# Disabled
-#config BOARD_AMD_BETTONG
-#	bool "Bettong"
diff --git a/src/mainboard/amd/bettong/Makefile.inc b/src/mainboard/amd/bettong/Makefile.inc
deleted file mode 100644
index cfcc9c0744..0000000000
--- a/src/mainboard/amd/bettong/Makefile.inc
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-romstage-y += boardid.c
-
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-ramstage-$(CONFIG_HUDSON_IMC_FWM) += fchec.c
-ramstage-y += boardid.c
diff --git a/src/mainboard/amd/bettong/OemCustomize.c b/src/mainboard/amd/bettong/OemCustomize.c
deleted file mode 100644
index 0e7882fb2e..0000000000
--- a/src/mainboard/amd/bettong/OemCustomize.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-#include <boardid.h>
-
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	/* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 3, 1,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x02, 0)
-	},
-
-	/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x03, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, 2, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x04, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x05, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x06, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */
-	{
-		DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags  !!!IMPORTANT!!! Terminate last element of array */
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x07, 0)
-	},
-
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* DP0 */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-	},
-	/* DP1 */
-	{
-		0, /*DESCRIPTOR_TERMINATE_LIST, */
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	},
-	/* DP2 */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList
-};
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      **PeiServices
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID OemCustomizeInitEarly (
-	IN  OUT AMD_EARLY_PARAMS    *InitEarly
-	)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-}
-
-static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
-	DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
-	MOTHER_BOARD_LAYERS(LAYERS_6),
-	MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
-	CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
-	ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
-	CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
-	PSO_END
-};
-
-void OemPostParams(AMD_POST_PARAMS *PostParams)
-{
-	if (board_id() == 'F') {
-		PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
-	}
-}
diff --git a/src/mainboard/amd/bettong/README b/src/mainboard/amd/bettong/README
deleted file mode 100644
index 631cf0f0ef..0000000000
--- a/src/mainboard/amd/bettong/README
+++ /dev/null
@@ -1,25 +0,0 @@
-coreboot is changing all the time and the patches are reabsed when pushed to
-community, so it is a little difficult to provide stable Bettong code.
-From now on, AMD provides source code which is validated by QA team.
-The code is pushed to github https://github.com/BTDC/coreboot
-The version is identified by a tag. All the changes will be pushed to coreboot
-community.
-
-=====
-Version: TCMEF1F0        Release Date: 09/29/2015
-
-Changes from last version:
-1. Fix external graphics issue.
-2. Add board ID support.
-3. Support DDR4.
-4. Support SD 2.0.
-5. Fix Windows 7 S4 issue.
-6. Add GPIO, I2C and UART support.
-7. Fix the interrupt routine.
-8. Restruct PCI interrupt table (C00/C01).
-9. Fix DSDT issue.
-10. Fix the PCIe lane map.
-11. Lower the TOM to give more MMIO space.
-12. Add USB device.
-13. Set the USB3 port as irremovable.
-14. Update AGESA to CarrizoPI 1.1.0.1.
diff --git a/src/mainboard/amd/bettong/acpi/carrizo_fch.asl b/src/mainboard/amd/bettong/acpi/carrizo_fch.asl
deleted file mode 100644
index 79f54203d2..0000000000
--- a/src/mainboard/amd/bettong/acpi/carrizo_fch.asl
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Device(GPIO) {
-	Name (_HID, "AMD0030")
-	Name (_CID, "AMD0030")
-	Name(_UID, 0)
-
-	Method (_CRS, 0x0, NotSerialized) {
-		Name (RBUF, ResourceTemplate () {
-			//
-			// Interrupt resource. In this example, banks 0 & 1 share the same
-			// interrupt to the parent controller and similarly banks 2 & 3.
-			//
-			// N.B. The definition below is chosen for an arbitrary
-			//      test platform. It needs to be changed to reflect the hardware
-			//      configuration of the actual platform
-			//
-			Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-
-			//
-			// Memory resource. The definition below is chosen for an arbitrary
-			// test platform. It needs to be changed to reflect the hardware
-			// configuration of the actual platform.
-			//
-			Memory32Fixed(ReadWrite, 0xFED81500, 0x300)
-		})
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0x0, NotSerialized) {
-			Return (0x0F)
-	}
-}
-
-Device(FUR0) {
-	Name(_HID,"AMD0020")
-	Name(_UID,0x0)
-	Name(_CRS, ResourceTemplate() {
-		IRQ(Edge, ActiveHigh, Exclusive) {10}
-		Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000)
-	})
-	Method (_STA, 0x0, NotSerialized) {
-		Return (0x0F)
-	}
-}
-
-Device(FUR1) {
-	Name(_HID,"AMD0020")
-	Name(_UID,0x1)
-	Name(_CRS, ResourceTemplate() {
-			IRQ(Edge, ActiveHigh, Exclusive) {11}
-			Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000)
-	})
-	Method (_STA, 0x0, NotSerialized) {
-			Return (0x0F)
-	}
-}
-
-Device(I2CA) {
-	Name(_HID,"AMD0010")
-	Name(_UID,0x0)
-	Name(_CRS, ResourceTemplate() {
-		IRQ(Edge, ActiveHigh, Exclusive) {3}
-		Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
-	})
-
-	Method (_STA, 0x0, NotSerialized) {
-		Return (0x0F)
-	}
-}
-
-Device(I2CB)
-{
-	Name(_HID,"AMD0010")
-	Name(_UID,0x1)
-	Name(_CRS, ResourceTemplate() {
-		IRQ(Edge, ActiveHigh, Exclusive) {15}
-		Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000)
-	})
-	Method (_STA, 0x0, NotSerialized) {
-		Return (0x0F)
-	}
-}
diff --git a/src/mainboard/amd/bettong/acpi/gpe.asl b/src/mainboard/amd/bettong/acpi/gpe.asl
deleted file mode 100644
index 87b0d2169d..0000000000
--- a/src/mainboard/amd/bettong/acpi/gpe.asl
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  General event 3  */
-	Method(_L03) {
-		/* DBGO("\\_GPE\\_L00\n") */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/bettong/acpi/mainboard.asl b/src/mainboard/amd/bettong/acpi/mainboard.asl
deleted file mode 100644
index db5731f088..0000000000
--- a/src/mainboard/amd/bettong/acpi/mainboard.asl
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Memory related values */
-Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-Name(PBLN, 0x0)	/* Length of BIOS area */
-
-Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
-Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
-Name(HPBA, 0xFED00000)	/* Base address of HPET table */
-
-/* Some global data */
-Name(OSVR, 3)	/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-Name(OSV, Ones)	/* Assume nothing */
-Name(PMOD, One)	/* Assume APIC */
diff --git a/src/mainboard/amd/bettong/acpi/routing.asl b/src/mainboard/amd/bettong/acpi/routing.asl
deleted file mode 100644
index 0c4edbbee9..0000000000
--- a/src/mainboard/amd/bettong/acpi/routing.asl
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Name(PR0, Package(){
-	/* NB devices */
-	/* Bus 0, Dev 0 - F16 Host Controller */
-
-	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-	/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
-	Package(){0x0001FFFF, 0, INTB, 0 },
-	Package(){0x0001FFFF, 1, INTC, 0 },
-
-
-	/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
-	Package(){0x0002FFFF, 0, INTC, 0 },
-	Package(){0x0002FFFF, 1, INTD, 0 },
-	Package(){0x0002FFFF, 2, INTA, 0 },
-	Package(){0x0002FFFF, 3, INTB, 0 },
-
-	/* FCH devices */
-	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
-	Package(){0x0014FFFF, 0, INTA, 0 },
-	Package(){0x0014FFFF, 1, INTB, 0 },
-	Package(){0x0014FFFF, 2, INTC, 0 },
-	Package(){0x0014FFFF, 3, INTD, 0 },
-
-	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
-	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
-	Package(){0x0012FFFF, 0, INTC, 0 },
-	Package(){0x0012FFFF, 1, INTB, 0 },
-
-	Package(){0x0013FFFF, 0, INTC, 0 },
-	Package(){0x0013FFFF, 1, INTB, 0 },
-
-	Package(){0x0016FFFF, 0, INTC, 0 },
-	Package(){0x0016FFFF, 1, INTB, 0 },
-
-	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, INTC, 0 },
-	Package(){0x0010FFFF, 1, INTB, 0 },
-
-	/* Bus 0, Dev 17 - SATA controller */
-	Package(){0x0011FFFF, 0, INTD, 0 },
-
-})
-
-Name(APR0, Package(){
-	/* NB devices in APIC mode */
-	/* Bus 0, Dev 0 - F15 Host Controller */
-
-	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-	Package(){0x0001FFFF, 0, 0, 43 },
-	Package(){0x0001FFFF, 1, 0, 40 },
-
-	/* Bus 0, Dev 2 - PCIe Bridges  */
-	Package(){0x0002FFFF, 0, 0, 44 },
-	Package(){0x0002FFFF, 1, 0, 45 },
-	Package(){0x0002FFFF, 2, 0, 46 },
-	Package(){0x0002FFFF, 3, 0, 47 },
-
-	Package(){0x0003FFFF, 0, 0, 49 },
-	Package(){0x0003FFFF, 1, 0, 50 },
-	Package(){0x0003FFFF, 2, 0, 51 },
-	Package(){0x0003FFFF, 3, 0, 52 },
-
-	Package(){0x0008FFFF, 0, 0, 35 },
-	Package(){0x0008FFFF, 1, 0, 32 },
-	Package(){0x0008FFFF, 2, 0, 33 },
-	Package(){0x0008FFFF, 3, 0, 34 },
-
-	/* SB devices in APIC mode */
-	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
-	Package(){0x0014FFFF, 0, 0, 16 },
-	Package(){0x0014FFFF, 1, 0, 17 },
-	Package(){0x0014FFFF, 2, 0, 18 },
-	Package(){0x0014FFFF, 3, 0, 19 },
-
-	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
-	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
-	Package(){0x0012FFFF, 0, 0, 18 },
-	Package(){0x0012FFFF, 1, 0, 17 },
-
-	Package(){0x0013FFFF, 0, 0, 18 },
-	Package(){0x0013FFFF, 1, 0, 17 },
-
-	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, 0, 18},
-	Package(){0x0010FFFF, 1, 0, 17},
-
-	/* Bus 0, Dev 17 - SATA controller */
-	Package(){0x0011FFFF, 0, 0, 19 },
-
-	/* Bus 0, Dev 9, Func 2 - HDAudio */
-	Package(){0x0009FFFF, 0, 0, 39 },
-	Package(){0x0009FFFF, 1, 0, 36 },
-	Package(){0x0009FFFF, 2, 0, 37 },
-	Package(){0x0009FFFF, 3, 0, 38 },
-})
-
-Name(PS2, Package(){
-	Package(){0x0000FFFF, 0, INTC, 0 },
-	Package(){0x0000FFFF, 1, INTD, 0 },
-	Package(){0x0000FFFF, 2, INTA, 0 },
-	Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS2, Package(){
-	Package(){0x0000FFFF, 0, 0, 18 },
-	Package(){0x0000FFFF, 1, 0, 19 },
-	Package(){0x0000FFFF, 2, 0, 16 },
-	Package(){0x0000FFFF, 3, 0, 17 },
-})
-
-/* GFX */
-Name(PS4, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS4, Package(){
-	/* PCIe slot - Hooked to PCIe slot 4 */
-	Package(){0x0000FFFF, 0, 0, 24 },
-	Package(){0x0000FFFF, 1, 0, 25 },
-	Package(){0x0000FFFF, 2, 0, 26 },
-	Package(){0x0000FFFF, 3, 0, 27 },
-})
-
-/* GPP 0 */
-Name(PS5, Package(){
-	Package(){0x0000FFFF, 0, INTB, 0 },
-	Package(){0x0000FFFF, 1, INTC, 0 },
-	Package(){0x0000FFFF, 2, INTD, 0 },
-	Package(){0x0000FFFF, 3, INTA, 0 },
-})
-Name(APS5, Package(){
-	Package(){0x0000FFFF, 0, 0, 28 },
-	Package(){0x0000FFFF, 1, 0, 29 },
-	Package(){0x0000FFFF, 2, 0, 30 },
-	Package(){0x0000FFFF, 3, 0, 31 },
-})
-
-/* GPP 1 */
-Name(PS6, Package(){
-	Package(){0x0000FFFF, 0, INTC, 0 },
-	Package(){0x0000FFFF, 1, INTD, 0 },
-	Package(){0x0000FFFF, 2, INTA, 0 },
-	Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS6, Package(){
-	Package(){0x0000FFFF, 0, 0, 32 },
-	Package(){0x0000FFFF, 1, 0, 33 },
-	Package(){0x0000FFFF, 2, 0, 34 },
-	Package(){0x0000FFFF, 3, 0, 35 },
-})
-
-/* GPP 2 */
-Name(PS7, Package(){
-	Package(){0x0000FFFF, 0, INTD, 0 },
-	Package(){0x0000FFFF, 1, INTA, 0 },
-	Package(){0x0000FFFF, 2, INTB, 0 },
-	Package(){0x0000FFFF, 3, INTC, 0 },
-})
-Name(APS7, Package(){
-	Package(){0x0000FFFF, 0, 0, 36 },
-	Package(){0x0000FFFF, 1, 0, 37 },
-	Package(){0x0000FFFF, 2, 0, 38 },
-	Package(){0x0000FFFF, 3, 0, 39 },
-})
-
-/* GPP 3 */
-Name(PS8, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS8, Package(){
-	Package(){0x0000FFFF, 0, 0, 40 },
-	Package(){0x0000FFFF, 1, 0, 41 },
-	Package(){0x0000FFFF, 2, 0, 42 },
-	Package(){0x0000FFFF, 3, 0, 43 },
-})
-
-/* GFX 2 */
-Name(PSA, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APSA, Package(){
-	Package(){0x0000FFFF, 0, 0, 52 },
-	Package(){0x0000FFFF, 1, 0, 53 },
-	Package(){0x0000FFFF, 2, 0, 54 },
-	Package(){0x0000FFFF, 3, 0, 55 },
-})
-
-/* GFX 3 */
-Name(PSB, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APSB, Package(){
-	Package(){0x0000FFFF, 0, 0, 27 },
-	Package(){0x0000FFFF, 1, 0, 24 },
-	Package(){0x0000FFFF, 2, 0, 25 },
-	Package(){0x0000FFFF, 3, 0, 26 },
-})
-
-/* GFX 4 */
-Name(PSC, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APSC, Package(){
-	Package(){0x0000FFFF, 0, 0, 31 },
-	Package(){0x0000FFFF, 1, 0, 28 },
-	Package(){0x0000FFFF, 2, 0, 29 },
-	Package(){0x0000FFFF, 3, 0, 30 },
-})
diff --git a/src/mainboard/amd/bettong/acpi/sleep.asl b/src/mainboard/amd/bettong/acpi/sleep.asl
deleted file mode 100644
index 58f0752f30..0000000000
--- a/src/mainboard/amd/bettong/acpi/sleep.asl
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Clear wake status structure. */
-	Store(0, PEWD)
-	Store(0, Index(WKST,0))
-	Store(0, Index(WKST,1))
-	Store(7, UPWS)
-} /* End Method(\_PTS) */
-
-/*
-*	\_BFS OEM Back From Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		-none-
-*/
-Method(\_BFS, 1) {
-	/* DBGO("\\_BFS\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-}
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/bettong/acpi/usb_oc.asl b/src/mainboard/amd/bettong/acpi/usb_oc.asl
deleted file mode 100644
index 328883af91..0000000000
--- a/src/mainboard/amd/bettong/acpi/usb_oc.asl
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-/* USB Overcurrent GPEs */
-
-#if 0 /* TODO: Update for Bettong */
-Method(UCOC, 0) {
-	Sleep(20)
-	Store(0x13,CMTI)
-	Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
-	Scope (\_GPE) {
-		Method (_L13) {
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
-	Scope (\_GPE) {
-		Method (_L14) {
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
-	Scope (\_GPE) {
-		Method (_L15) {
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
-	Scope (\_GPE) {
-		Method (_L16) {
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
-	Scope (\_GPE) {
-		Method (_L19) {
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
-	Scope (\_GPE) {
-		Method (_L17) {
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-		}
-	}
-}
-#endif
diff --git a/src/mainboard/amd/bettong/acpi_tables.c b/src/mainboard/amd/bettong/acpi_tables.c
deleted file mode 100644
index 9117c1ffdf..0000000000
--- a/src/mainboard/amd/bettong/acpi_tables.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-
-#define IO_APIC2_ADDR 0xFEC20000
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write Kern IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-					   IO_APIC_ADDR, 0);
-
-	/* TODO: Remove the hardcode */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
-					   IO_APIC2_ADDR, 24);
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, 0xF);
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
diff --git a/src/mainboard/amd/bettong/board_info.txt b/src/mainboard/amd/bettong/board_info.txt
deleted file mode 100644
index b351b8e696..0000000000
--- a/src/mainboard/amd/bettong/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/amd/bettong/boardid.c b/src/mainboard/amd/bettong/boardid.c
deleted file mode 100644
index 21d0476204..0000000000
--- a/src/mainboard/amd/bettong/boardid.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <amdblocks/acpimmio.h>
-#include <device/mmio.h>
-#include <southbridge/amd/common/amd_defs.h>
-#include <boardid.h>
-
-/**
- *Bettong uses 3 GPIO(5-7) pins to identify board.
- *The GPIO ports are mapped to MMIO space.
- *The GPIO value and board version are mapped as follow:
- *GPIO5 GPIO6 GPIO7 Version
- *  0     0     0      A
- *  0     0     1      B
- *  ......
- *  1     1     1      H
- */
-uint32_t board_id(void)
-{
-	u8  value = 0;
-	u8  boardrev = 0;
-	char boardid;
-
-	value = gpio0_read8((7 << 2) + 2); /* agpio7: board_id2 */
-	boardrev = value & 1;
-	value = gpio0_read8((6 << 2) + 2); /* agpio6: board_id1 */
-	boardrev |= (value & 1) << 1;
-	value = gpio0_read8((5 << 2) + 2); /* agpio5: board_id0 */
-	boardrev |= (value & 1) << 2;
-
-	boardid = 'A' + boardrev;
-
-	return boardid;
-}
diff --git a/src/mainboard/amd/bettong/cmos.layout b/src/mainboard/amd/bettong/cmos.layout
deleted file mode 100644
index 49878e25b1..0000000000
--- a/src/mainboard/amd/bettong/cmos.layout
+++ /dev/null
@@ -1,101 +0,0 @@
-#*****************************************************************************
-#
-#  This file is part of the coreboot project.
-#
-#  Copyright (C) 2015 Advanced Micro Devices, Inc.
-#
-#  This program is free software; you can redistribute it and/or modify
-#  it under the terms of the GNU General Public License as published by
-#  the Free Software Foundation; version 2 of the License.
-#
-#  This program is distributed in the hope that it will be useful,
-#  but WITHOUT ANY WARRANTY; without even the implied warranty of
-#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#  GNU General Public License for more details.
-#*****************************************************************************
-
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-#96         288       r       0        temporary_filler
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-386          1       e       1        ECC_memory
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-416          4       e       7        boot_first
-420          4       e       7        boot_second
-424          4       e       7        boot_third
-428          4       h       0        boot_index
-432          8       h       0        boot_countdown
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-7     0     Network
-7     1     HDD
-7     2     Floppy
-7     8     Fallback_Network
-7     9     Fallback_HDD
-7     10    Fallback_Floppy
-#7     3     ROM
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb
deleted file mode 100644
index c447bcad95..0000000000
--- a/src/mainboard/amd/bettong/devicetree.cb
+++ /dev/null
@@ -1,67 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/amd/pi/00660F01/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/pi/00660F01
-			device lapic 10 on end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-
-		chip northbridge/amd/pi/00660F01
-			device pci 0.0 on  end # Root Complex
-			device pci 1.0 on  end # Internal Graphics P2P bridge 0x9804
-			device pci 1.1 on  end # Internal Multimedia
-			device pci 2.0 on  end # PCIe Host Bridge
-			device pci 2.1 on  end # x4 PCIe slot
-			device pci 2.2 on  end # mPCIe slot
-			device pci 2.3 on  end # Realtek NIC
-			device pci 2.4 on  end # Edge Connector
-			device pci 2.5 on  end # Edge Connector
-			device pci 3.0 on  end # Edge Connector
-			device pci 3.1 on  end # Edge Connector
-		end	#chip northbridge/amd/pi/00660F01
-
-		chip southbridge/amd/pi/hudson
-			device pci 9.0 on  end # HDA
-			device pci 9.2 on  end # HDA
-			device pci 10.0 on  end # USB
-			device pci 11.0 on  end # SATA
-			device pci 12.0 on  end # USB
-			device pci 14.0 on  end # SM
-			#device pci 14.2 on  end # HDA	0x4383
-			device pci 14.3 on  end # LPC	0x439d
-			device pci 14.7 on  end # SD
-		end	#chip southbridge/amd/pi/hudson
-
-		chip northbridge/amd/pi/00660F01
-			device pci 18.0 on  end
-			device pci 18.1 on  end
-			device pci 18.2 on  end
-			device pci 18.3 on  end
-			device pci 18.4 on  end
-			device pci 18.5 on  end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-		end
-
-	end #domain
-end #northbridge/amd/pi/00660F01/root_complex
diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl
deleted file mode 100644
index f6449ece99..0000000000
--- a/src/mainboard/amd/bettong/dsdt.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-#include <arch/acpi.h>
-DefinitionBlock (
-	"DSDT.AML",	/* Output filename */
-	"DSDT",		/* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
-
-	/* Globals for the platform */
-	#include "acpi/mainboard.asl"
-
-	/* Describe the USB Overcurrent pins */
-	#include "acpi/usb_oc.asl"
-
-	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
-
-	/* Describe the processor tree (\_PR) */
-	#include <cpu/amd/pi/00660F01/acpi/cpu.asl>
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
-		#include "acpi/routing.asl"
-
-		Device(PWRB) {
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})
-			Name(_STA, 0x0B)
-		}
-
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/pi/00660F01/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/pi/hudson/acpi/fch.asl>
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
-
-		/* Describe the devices in the Southbridge */
-		#include "acpi/carrizo_fch.asl"
-
-	} /* End \_SB scope */
-
-	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
-
-	/* Define the General Purpose Events for the platform */
-	#include "acpi/gpe.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/bettong/fchec.c b/src/mainboard/amd/bettong/fchec.c
deleted file mode 100644
index ea7dc569c7..0000000000
--- a/src/mainboard/amd/bettong/fchec.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "fchec.h"
-
-void agesawrapper_fchecfancontrolservice()
-{
-	FCH_DATA_BLOCK LateParams;
-
-	/* Thermal Zone Parameter */
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
-
-	/* IMC Fan Policy temperature thresholds */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold in Celsius */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 threshold in Celsius */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 threshold in Celsius */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
-
-	/* IMC Fan Policy PWM Settings */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
-
-	LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111;
-
-	FchECfancontrolservice(&LateParams);
-}
diff --git a/src/mainboard/amd/bettong/irq_tables.c b/src/mainboard/amd/bettong/irq_tables.c
deleted file mode 100644
index 7334bb2fd8..0000000000
--- a/src/mainboard/amd/bettong/irq_tables.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c
deleted file mode 100644
index 8e2ecfd8e1..0000000000
--- a/src/mainboard/amd/bettong/mainboard.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- */
-static const u8 mainboard_picr_data[] = {
-	[0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
-	[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	[0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
-	[0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
-	[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,
-	[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
-	[0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
-	[0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-};
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
-	[0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
-	[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
-	[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,
-	[0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00,
-	[0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
-	[0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-
-
-/*************************************************
- * enable the dedicated function in bettong board.
- *************************************************/
-static void bettong_enable(struct device *dev)
-{
-	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = bettong_enable,
-};
diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c
deleted file mode 100644
index d9632d58d1..0000000000
--- a/src/mainboard/amd/bettong/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
-	mc->mpc_length += length;
-	mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
-			     unsigned char id, const char *bustype)
-{
-	struct mpc_config_bus *mpc;
-	mpc = smp_next_mpc_entry(mc);
-	memset(mpc, '\0', sizeof(*mpc));
-	mpc->mpc_type = MP_BUS;
-	mpc->mpc_busid = id;
-	memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
-	smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	/*
-	 * By the time this function gets called, the IOAPIC registers
-	 * have been written so they can be read to get the correct
-	 * APIC ID and Version
-	 */
-	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-	memcpy(mc->mpc_oem, "AMD     ", 8);
-
-	smp_write_processors(mc);
-
-	my_smp_write_bus(mc, 0, "PCI   ");
-	my_smp_write_bus(mc, 1, "PCI   ");
-	bus_isa = 0x02;
-	my_smp_write_bus(mc, bus_isa, "ISA   ");
-
-	/* I/O APICs:   APIC ID Version State   Address */
-	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
-	smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin)				\
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#define PCI_INT(bus, dev, int_sign, pin)				\
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
-	/* Internal VGA */
-	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
-	PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
-	/* SMBUS */
-	PCI_INT(0x0, 0x14, 0x0, 0x10);
-
-	/* HD Audio */
-	PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
-	/* USB */
-	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
-	PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
-	PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
-	PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
-	PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
-	/* sata */
-	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
-	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
-	/* on board NIC & Slot PCIE.  */
-
-	/* PCI slots */
-	struct device *dev = pcidev_on_root(0x14, 4);
-	if (dev && dev->enabled) {
-		u8 bus_pci = dev->link_list->secondary;
-		/* PCI_SLOT 0. */
-		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
-		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
-		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
-		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
-		/* PCI_SLOT 1. */
-		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
-		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
-		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
-		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
-		/* PCI_SLOT 2. */
-		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
-		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
-		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
-		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
-	}
-
-	/* PCIe Lan*/
-	PCI_INT(0x0, 0x06, 0x0, 0x13);
-
-	/* FCH PCIe PortA */
-	PCI_INT(0x0, 0x15, 0x0, 0x10);
-	/* FCH PCIe PortB */
-	PCI_INT(0x0, 0x15, 0x1, 0x11);
-	/* FCH PCIe PortC */
-	PCI_INT(0x0, 0x15, 0x2, 0x12);
-	/* FCH PCIe PortD */
-	PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
deleted file mode 100644
index 0f41f714e3..0000000000
--- a/src/mainboard/amd/bettong/romstage.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-/* Mask BIST bit 31. One result of Silicon Observation
- * report_bist_failure(bist & 0x7FFFFFFF);
- */
-
-static void romstage_main_template(void)
-{
-	u32 val;
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
-
-#if CONFIG(HUDSON_UART)
-		configure_hudson_uart();
-#endif
-		post_code(0x31);
-		console_init();
-	}
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
-	/* After AMD_INIT_ENV -> move to ramstage ? */
-	if (acpi_is_wakeup_s4()) {
-		outb(0xEE, PM_INDEX);
-		outb(0x8, PM_DATA);
-	}
-}