diff options
| author | Ashish Kumar Mishra <ashish.k.mishra@intel.com> | 2024-03-28 14:49:32 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-17 17:52:10 +0000 |
| commit | 2ed80b16b3099c827bb76baa1976625d4b574e24 (patch) | |
| tree | fb0709b03a4d1ef51cc9fe3caa0dfa787579fef1 /src/mainboard | |
| parent | 055c6d5c349c6e12842d4ba6cf4235642dabc3de (diff) | |
mb/google/brox: Enable SAGv
Enable SaGv support for brox
BUG=None
BRANCH=None
TEST=Boot brox with SAGv enabled and verify in fsp debug logs
Change-Id: I80c44e7df1d75732c6982b27e44ecd6060b1b3f1
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81556
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 9ed0602e2e..f901db9735 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -11,6 +11,9 @@ chip soc/intel/alderlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Enable SAGv + register "sagv" = "SaGv_Enabled" + # S0ix enable register "s0ix_enable" = "1" |