diff options
| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-09-07 16:25:52 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-30 16:51:00 +0000 |
| commit | 2ddcf409c3b79672665163e7a826991779dd620e (patch) | |
| tree | a901f52450e223f61c6cd5a895f22b01bc728853 /src/mainboard | |
| parent | 1ec8f97782060757dc8d2df2ff1c022039b225f8 (diff) | |
mb/prodrive/atlas: Add Kconfig option to enable SaGv
It turns out that one can use Kconfig options to specify values for
devicetree options, as long as the resulting expression is a compile
time constant. Use this to configure SaGv for Atlas: enable it by
default, but allow SaGv to be disabled manually for convenience when
testing. Enabling SaGv makes MRC train the RAM multiple times, which
takes a significant amount of time.
For further info on SAGV on ADL, please refer to Intel Doc 655258
(Alder Lake Datasheet) section 5.1.3.2.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I3c6ac25d414122c408f2348d12dba8dce909e567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/prodrive/atlas/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/prodrive/atlas/devicetree.cb | 3 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig index 38d600c480..ce9aeab4e6 100644 --- a/src/mainboard/prodrive/atlas/Kconfig +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -16,6 +16,10 @@ config BOARD_PRODRIVE_ATLAS_BASEBOARD if BOARD_PRODRIVE_ATLAS_BASEBOARD +config ATLAS_ENABLE_SAGV + bool "Enable SaGv" + default y + config MAINBOARD_FAMILY string default "PRODRIVE_ATLAS_SERIES" diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 42d5b44c37..6e795a77d3 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -14,6 +14,9 @@ chip soc/intel/alderlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # SaGv Configuration + register "sagv" = "CONFIG(ATLAS_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled" + # Display configuration (4 DPs) register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, |