mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670

It is a new incoming Protectli product based on Alder Lake-P SoC.
More details and documentation will be added later.

TEST=Boot Ubuntu 22.04 LTS and Windows 11 on VP6670.

Change-Id: If4ae5b14b69806b6b0727d1ca1dcf56f47cfcd8e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80501
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

18 files changed, 1268 insertions, 0 deletions

diff --git a/src/mainboard/protectli/vault_adl_p/Kconfig b/src/mainboard/protectli/vault_adl_p/Kconfig
new file mode 100644
index 0000000000..51fb7c5b91
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/Kconfig
@@ -0,0 +1,81 @@
+if BOARD_PROTECTLI_VP66XX
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SUPERIO_ITE_IT8659E
+	select DRIVERS_UART_8250IO
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_INTEL_PMC
+	select FSP_TYPE_IOT	# Needed for PchPcieClockGating W/A
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select MEMORY_MAPPED_TPM
+	select USE_DDR5
+
+config MAINBOARD_DIR
+	default "protectli/vault_adl_p"
+
+config MAINBOARD_PART_NUMBER
+	default "VP66XX"
+
+config MAINBOARD_VENDOR
+	default "Protectli"
+
+config MAINBOARD_FAMILY
+	default "Vault Pro"
+
+config DIMM_SPD_SIZE
+	default 1024
+
+config DIMM_MAX
+	default 2
+
+config USE_PM_ACPI_TIMER
+	default n
+
+config CBFS_SIZE
+	default 0xa80000
+
+config TPM_PIRQ
+	default 0x39	# GPP_E13_IRQ
+
+# CLKREQ pins not connected, so disable L1 and CPM
+config PCIEXP_L1_SUB_STATE
+	default n
+
+config PCIEXP_CLK_PM
+	default n
+
+config VBOOT
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_FWMP
+	select GBB_FLAG_DISABLE_LID_SHUTDOWN
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select VBOOT_ALWAYS_ENABLE_DISPLAY
+	select VBOOT_NO_BOARD_SUPPORT
+	select HAS_RECOVERY_MRC_CACHE
+	select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE
+
+config VBOOT_SLOTS_RW_A
+	default y if VBOOT
+
+config SOC_INTEL_CSE_SEND_EOP_EARLY
+	default n
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A
+
+config BEEP_ON_BOOT
+	bool "Beep on successful boot"
+	default y
+	help
+	  Make the platform beep using the PC speaker in final coreboot phase.
+	  May serve as a useful indicator in headless mode that platform is
+	  properly booting.
+
+endif
diff --git a/src/mainboard/protectli/vault_adl_p/Kconfig.name b/src/mainboard/protectli/vault_adl_p/Kconfig.name
new file mode 100644
index 0000000000..4888042353
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_PROTECTLI_VP66XX
+	bool "VP6630/VP6650/VP6670"
diff --git a/src/mainboard/protectli/vault_adl_p/Makefile.mk b/src/mainboard/protectli/vault_adl_p/Makefile.mk
new file mode 100644
index 0000000000..5611ca5a64
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/Makefile.mk
@@ -0,0 +1,14 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += gpio.c
+romstage-y += romstage_fsp_params.c
+
+ramstage-y += mainboard.c
+
+all-y += die.c
+smm-y += die.c
+
+all-y += board_beep.c
+smm-y += board_beep.c
diff --git a/src/mainboard/protectli/vault_adl_p/acpi/superio.asl b/src/mainboard/protectli/vault_adl_p/acpi/superio.asl
new file mode 100644
index 0000000000..cf5a2c5d5f
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/acpi/superio.asl
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x2e
+#define IT8659E_SHOW_UARTA
+#define IT8659E_SHOW_UARTB
+
+#define IT8659E_EC_IO0
+#define IT8659E_EC_IO1
+#define IT8659E_SHOW_EC
+
+#define IT8659E_GPIO_IO0
+#define IT8659E_GPIO_IO1
+#define IT8659E_SHOW_GPIO
+
+#include <superio/ite/it8659e/acpi/superio.asl>
diff --git a/src/mainboard/protectli/vault_adl_p/board_beep.c b/src/mainboard/protectli/vault_adl_p/board_beep.c
new file mode 100644
index 0000000000..76cda26407
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/board_beep.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <delay.h>
+
+#include "board_beep.h"
+
+#define ITE_GPIO_BASE		0xa00
+#define ITE_GPIO_PIN(x)		(1 << ((x) % 10))
+#define ITE_GPIO_SET(x)		(((x) / 10) - 1)
+#define ITE_GPIO_IO_ADDR(x)	(ITE_GPIO_BASE + ITE_GPIO_SET(x))
+
+void do_beep(uint32_t frequency, uint32_t duration_msec)
+{
+	uint32_t timer_delay = 1000000 / frequency / 2;
+	uint32_t count = (duration_msec * 1000) / (timer_delay * 2);
+	uint8_t val = inb(ITE_GPIO_IO_ADDR(41)); /* GP41 drives a MOSFET for PC Speaker */
+
+	for (uint32_t i = 0; i < count; i++) {
+		outb(val | ITE_GPIO_PIN(41), ITE_GPIO_IO_ADDR(41));
+		udelay(timer_delay);
+		outb(val & ~ITE_GPIO_PIN(41), ITE_GPIO_IO_ADDR(41));
+		udelay(timer_delay);
+	}
+}
diff --git a/src/mainboard/protectli/vault_adl_p/board_beep.h b/src/mainboard/protectli/vault_adl_p/board_beep.h
new file mode 100644
index 0000000000..956c9393ab
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/board_beep.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef BOARD_BEEP_H
+#define BOARD_BEEP_H
+
+void do_beep(uint32_t frequency, uint32_t duration_msec);
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/protectli/vault_adl_p/board_info.txt b/src/mainboard/protectli/vault_adl_p/board_info.txt
new file mode 100644
index 0000000000..963a0aef67
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/board_info.txt
@@ -0,0 +1,7 @@
+Category: sbc
+Board URL: TBD
+ROM IC: Macronix KH25L12835F
+ROM package: SOIC8-8
+ROM socketed: no
+Flashrom support: yes
+Release year: 2024
diff --git a/src/mainboard/protectli/vault_adl_p/bootblock.c b/src/mainboard/protectli/vault_adl_p/bootblock.c
new file mode 100644
index 0000000000..becc634eb7
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/bootblock.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/common/ite_gpio.h>
+#include <superio/ite/it8659e/it8659e.h>
+
+#if CONFIG_UART_FOR_CONSOLE == 0
+#define UART_DEV PNP_DEV(0x2e, IT8659E_SP1)
+#elif CONFIG_UART_FOR_CONSOLE == 1
+#define UART_DEV PNP_DEV(0x2e, IT8659E_SP2)
+#else
+#error "Wrong UART_FOR_CONSOLE setting"
+#endif
+
+#define GPIO_DEV PNP_DEV(0x2e, IT8659E_GPIO)
+
+static void ite_set_gpio_iobase(u16 iobase)
+{
+	pnp_enter_conf_state(GPIO_DEV);
+	pnp_set_logical_device(GPIO_DEV);
+	pnp_set_iobase(GPIO_DEV, PNP_IDX_IO1, iobase);
+	pnp_exit_conf_state(GPIO_DEV);
+}
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Internal VCC_OK */
+	ite_reg_write(GPIO_DEV, 0x23, 0x40);
+	/* Set pin native functions */
+	ite_reg_write(GPIO_DEV, 0x26, 0xc0);
+	/* Pin28 as GP41 - PC speaker */
+	ite_reg_write(GPIO_DEV, 0x28, 0x02);
+	/* Set GPIOs exposed on pin header as GPIO functions */
+	ite_reg_write(GPIO_DEV, 0x29, 0xc0);
+	/* Sets a reserved bit6 to reflect original FW configuration */
+	ite_reg_write(GPIO_DEV, 0x2c, 0xc9);
+	ite_kill_watchdog(GPIO_DEV);
+	/* GP41 - PC Speaker configuration */
+	ite_gpio_setup(GPIO_DEV, 41, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE,
+		       ITE_GPIO_CONTROL_DEFAULT);
+	ite_set_gpio_iobase(0xa00);
+	ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/protectli/vault_adl_p/data.vbt b/src/mainboard/protectli/vault_adl_p/data.vbt
new file mode 100644
index 0000000000..6a36596d2b
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/data.vbt
diff --git a/src/mainboard/protectli/vault_adl_p/devicetree.cb b/src/mainboard/protectli/vault_adl_p/devicetree.cb
new file mode 100644
index 0000000000..f11dc6aba2
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/devicetree.cb
@@ -0,0 +1,324 @@
+chip soc/intel/alderlake
+	# FSP configuration
+
+	register "eist_enable" = "1"
+
+	# Sagv Configuration
+	register "sagv" = "SaGv_Enabled"
+	register "RMT" = "0"
+	register "enable_c6dram" = "1"
+
+	register "common_soc_config" = "{
+		// Type-C PD I2C bus
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	register "tcc_offset" = "20" # TCC of 80C
+
+	device domain 0 on
+		subsystemid 0x8086 0x7270 inherit
+
+		device ref pcie4_0 on
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_aspm = ASPM_L0S_L1,
+				.PcieRpL1Substates = L1_SS_DISABLED,
+				.clk_src = 3,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
+					 "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X"
+		end
+		device ref igpu on
+			subsystemid 0x8086 0x2212
+			register "ddi_portA_config" = "1" # HDMI on port A
+			register "ddi_portB_config" = "1" # DP on port B
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_3] = DDI_ENABLE_HPD,
+			}"
+		end
+		device ref tcss_xhci on
+			register "tcss_ports" = "{
+				[0] = TCSS_PORT_DEFAULT(OC_SKIP), // 5G module
+				[1] = TCSS_PORT_DEFAULT(OC_SKIP), // USB2.0 + USB 3.0 column with RJ45
+				[2] = TCSS_PORT_DEFAULT(OC_SKIP), // USB Type-C no TBT
+				[3] = TCSS_PORT_DEFAULT(OC_SKIP), // USB-A 3.0
+			}"
+
+			# SOC Aux orientation override:
+			# This is a bitfield that corresponds to up to 4 TCSS ports.
+			# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+			# Bits (4,5) allocated for TCSS Port3 configuration and Bits (6,7)for TCSS Port4.
+			# Bit0,Bit2,Bit4,Bit6 set to "1" indicates no retimer on USBC Ports
+			# Bit1,Bit3,Bit5,Bit7 set to "0" indicates Aux lines are not swapped on the
+			# motherboard to USBC connector
+			register "tcss_aux_ori" = "0x10"
+			register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
+
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 5G (MKB_4G1)""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1 (USB1)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
+						device ref tcss_usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref tcss_usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Internal""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref tcss_usb3_port4 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_SHORT(OC_SKIP),  // USB-A 2.0 USB1
+				[1] = USB2_PORT_SHORT(OC_SKIP),  // USB-A 3.0 USB1
+				[2] = USB2_PORT_SHORT(OC_SKIP),  // 5G
+				[3] = USB2_PORT_SHORT(OC_SKIP),  // USB-A 3.0 internal
+				[5] = USB2_PORT_SHORT(OC_SKIP),  // USB-A 2.0 USB2
+				[7] = USB2_PORT_TYPE_C(OC_SKIP), // USB Type-C no TBT
+				[8] = USB2_PORT_SHORT(OC_SKIP),  // USB-A 2.0 USB2
+				[9] = USB2_PORT_SHORT(OC_SKIP),  // WiFi slot
+			}"
+
+			# PCH USB3.x ports not used
+
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 2 (USB1)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Port 1 (USB1)""
+						register "type" = "UPC_TYPE_USB3_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 5G (MKB_4G1)""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Internal""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 4 (USB2)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(3, 1))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Port 3 (USB2)""
+						register "type" = "UPC_TYPE_A"
+						register "use_custom_pld" = "true"
+						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(3, 2))"
+						register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 WiFi/Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+				end
+			end
+		end
+		device ref i2c1 on
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+			chip drivers/i2c/generic
+				register "hid" = ""INT3515""
+				register "uid" = "1"
+				register "name" = ""PD01""
+				register "desc" = ""TPS65994 USB-C PD Controller""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E2)"
+				device i2c 23 on end
+			end
+		end
+		device ref sata on
+			register "sata_salp_support" = "1"
+
+			register "sata_ports_enable" = "{
+				[0] = 1,
+				[1] = 1,
+			}"
+		end
+		# x4 link to Intel XL710 2xSFP
+		device ref pcie_rp1 on
+			register "pch_pcie_rp[PCH_RP(1)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_aspm = ASPM_L0S_L1,
+				.PcieRpL1Substates = L1_SS_DISABLED,
+				.clk_src = 1,
+			}"
+		end
+		# RP5-RP8 i226 LAN
+		device ref pcie_rp5 on
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L0S_L1,
+				.PcieRpL1Substates = L1_SS_DISABLED,
+				.clk_src = 2,
+				.clk_req = 2,
+			}"
+		end
+		device ref pcie_rp6 on
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L0S_L1,
+				.PcieRpL1Substates = L1_SS_DISABLED,
+				.clk_src = 0,
+				.clk_req = 0,
+			}"
+		end
+		device ref pcie_rp7 on
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_aspm = ASPM_L0S_L1,
+				.PcieRpL1Substates = L1_SS_DISABLED,
+				.clk_src = 6,
+			}"
+		end
+		device ref pcie_rp8 on
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_aspm = ASPM_L0S_L1,
+				.PcieRpL1Substates = L1_SS_DISABLED,
+				.clk_src = 5,
+			}"
+		end
+		device ref pcie_rp10 on
+			register "pch_pcie_rp[PCH_RP(10)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_aspm = ASPM_L0S_L1,
+				.PcieRpL1Substates = L1_SS_DISABLED,
+				.clk_src = 4,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device pci 00.0 on end
+			end
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
+					 "M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X"
+		end
+		device ref pch_espi on
+			# LPC generic I/O ranges
+			register "gen1_dec" = "0x00fc0201"
+			register "gen2_dec" = "0x003c0a01"
+			register "gen3_dec" = "0x000c0081"
+
+			chip superio/ite/it8659e
+				register "TMPIN1.mode"    = "THERMAL_PECI"
+				register "TMPIN1.offset"  = "0x56"
+				register "ec.vin_mask"    = "VIN0 | VIN2 | VIN3 | VIN7"
+
+				# FAN1 is CPU fan (connector on board)
+				register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+				register "FAN1.smart.tmpin"     = " 1"
+				register "FAN1.smart.tmp_off"   = "40"
+				register "FAN1.smart.tmp_start" = "50"
+				register "FAN1.smart.tmp_full"  = "85"
+				register "FAN1.smart.pwm_start" = "20"
+				register "FAN1.smart.slope"     = "32"
+				# FAN2 is CPU fan (connector on board)
+				register "FAN2.mode" = "FAN_SMART_AUTOMATIC"
+				register "FAN2.smart.tmpin"     = " 1"
+				register "FAN2.smart.tmp_off"   = "40"
+				register "FAN2.smart.tmp_start" = "50"
+				register "FAN2.smart.tmp_full"  = "85"
+				register "FAN2.smart.pwm_start" = "20"
+				register "FAN2.smart.slope"     = "32"
+
+				device pnp 2e.1 on	# COM 1
+					io 0x60 = 0x3f8
+					irq 0x70 = 4
+					irq 0xf1 = 0x52 # IRQ low level
+				end
+				device pnp 2e.2 on	# COM 2
+					io 0x60 = 0x2f8
+					irq 0x70 = 3
+					irq 0xf1 = 0x52 # IRQ low level
+				end
+				device pnp 2e.4 on	# Environment Controller
+					io 0x60 = 0xa20
+					io 0x62 = 0xa10
+					irq 0x70 = 0	# Don't use IRQ
+					irq 0xf4 = 0x20 # PSON_N is inverted SUSB_N
+					irq 0xfa = 0x20 # Enable WDT output through PWRGD
+				end
+				device pnp 2e.5 off end	# Keyboard
+				device pnp 2e.6 off end	# Mouse
+				device pnp 2e.7 on	# GPIO
+					io 0x60 = 0xa08
+					io 0x62 = 0xa00
+				end
+				device pnp 2e.a off end	# CIR
+			end
+			chip drivers/pc80/tpm
+				device pnp 0.0 on end
+			end
+
+		end
+		device ref pmc hidden
+			register "pmc_gpe0_dw0" = "PMC_GPP_A"
+			register "pmc_gpe0_dw1" = "PMC_GPP_R"
+			register "pmc_gpe0_dw2" = "PMC_GPD"
+
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port8 as usb2_port
+						use tcss_usb3_port3 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref hda on
+			register "pch_hda_audio_link_hda_enable" = "1"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_codec_enable" = "true"
+		end
+		device ref smbus on end
+	end
+end
diff --git a/src/mainboard/protectli/vault_adl_p/die.c b/src/mainboard/protectli/vault_adl_p/die.c
new file mode 100644
index 0000000000..838572df5d
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/die.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <delay.h>
+#include <gpio.h>
+
+#include "board_beep.h"
+
+static void beep_and_blink(void)
+{
+	static uint8_t blink = 0;
+	static uint8_t beep_count = 0;
+
+	gpio_set(GPP_B14, blink);
+	/* Beep 12 times at most, constant beeps may be annoying */
+	if (beep_count < 12) {
+		do_beep(800, 300);
+		mdelay(200);
+		beep_count++;
+	} else {
+		mdelay(500);
+	}
+
+	blink ^= 1;
+}
+
+void die_notify(void)
+{
+	if (ENV_POSTCAR)
+		return;
+
+	/* Make SATA LED blink and use PC SPKR */
+	gpio_output(GPP_B14, 0);
+
+	while (1) {
+		beep_and_blink();
+		beep_and_blink();
+		beep_and_blink();
+		beep_and_blink();
+		delay(2);
+	}
+}
diff --git a/src/mainboard/protectli/vault_adl_p/dsdt.asl b/src/mainboard/protectli/vault_adl_p/dsdt.asl
new file mode 100644
index 0000000000..a6e97c4ceb
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/dsdt.asl
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+		#include <soc/intel/alderlake/acpi/tcss.asl>
+	}
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include "acpi/superio.asl"
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/protectli/vault_adl_p/gpio.c b/src/mainboard/protectli/vault_adl_p/gpio.c
new file mode 100644
index 0000000000..1e65f03a54
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/gpio.c
@@ -0,0 +1,453 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <gpio.h>
+
+#include "gpio.h"
+
+#ifndef PAD_CFG_GPIO_BIDIRECT
+#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own)		\
+	_PAD_CFG_STRUCT(pad,						\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) |	\
+		PAD_BUF(NO_DISABLE) | val,				\
+		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
+#endif
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_B ------- */
+
+	/* GPP_B0 - CORE_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	/* GPP_B1 - CORE_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	PAD_NC(GPP_B2, NONE),
+	PAD_NC(GPP_B3, NONE),
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_NC(GPP_B9, NONE),
+	PAD_NC(GPP_B10, NONE),
+	/* GPP_B11 - PMCALERT# */
+	PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1),
+	/* GPP_B12 - SLP_S0# */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13 - PLTRST# */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14 - SATA_LED# */
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF4),
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	/* GPP_B23 - GPIO */
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+	/* GPP_B24 - GSPI0_CLK_LOOPBK */
+	PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1),
+	/* GPP_B25 - GSPI1_CLK_LOOPBK */
+	PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group GPP_T ------- */
+
+	PAD_NC(GPP_T0, NONE),
+	PAD_NC(GPP_T1, NONE),
+	/* GPP_T2 - Reserved */
+	PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2),
+	/* GPP_T3 - Reserved */
+	PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2),
+	PAD_NC(GPP_T4, NONE),
+	PAD_NC(GPP_T5, NONE),
+	PAD_NC(GPP_T6, NONE),
+	PAD_NC(GPP_T7, NONE),
+	PAD_NC(GPP_T8, NONE),
+	PAD_NC(GPP_T9, NONE),
+	PAD_NC(GPP_T10, NONE),
+	PAD_NC(GPP_T11, NONE),
+	PAD_NC(GPP_T12, NONE),
+	PAD_NC(GPP_T13, NONE),
+	PAD_NC(GPP_T14, NONE),
+	PAD_NC(GPP_T15, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+
+	/* GPP_A0 - ESPI_IO0 */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+	/* GPP_A1 - ESPI_IO1 */
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+	/* GPP_A2 - ESPI_IO2 */
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+	/* GPP_A3 - ESPI_IO3 */
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+	/* GPP_A4 - ESPI_CS0# */
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+	/* GPP_A5 - ESPI_ALERT0# */
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	/* GPP_A9 - ESPI_CLK */
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	/* GPP_A10 - ESPI_RESET# */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_NC(GPP_A13, NONE),
+	/* GPP_A14 - DDSP_HPD3 */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2),
+	PAD_NC(GPP_A15, NONE),
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	/* GPP_A18 - DDSP_HPDB */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	/* GPP_A21 - USB_C_GPP_A21 */
+	PAD_CFG_NF(GPP_A21, NONE, PLTRST, NF6),
+	/* GPP_A22 - USB_C_GPP_A22 */
+	PAD_CFG_NF(GPP_A22, NONE, PLTRST, NF6),
+	/* GPP_A23 - ESPI_CS1# */
+	PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),
+	/* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */
+	PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_S ------- */
+
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+
+	PAD_NC(GPP_H0, NONE),
+	PAD_NC(GPP_H1, NONE),
+	PAD_NC(GPP_H2, NONE),
+	PAD_NC(GPP_H3, NONE),
+	PAD_NC(GPP_H4, NONE),
+	PAD_NC(GPP_H5, NONE),
+	/* GPP_H6 - I2C1_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* GPP_H7 - I2C1_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE),
+	/* GPP_H15 - DDPB_CTRLCLK */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* GPP_H16 - GPIO */
+	PAD_NC(GPP_H16, NONE),
+	/* GPP_H17 - DDPB_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H18 - PROC_C10_GATE# */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* GPP_H19 - originally SRCCLKREQ4# but NC on schematics */
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	/* GPP_D5 - SRCCLKREQ0# to PCIE RP 6 */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	PAD_NC(GPP_D6, NONE),
+	/* GPP_D7 - SRCCLKREQ2# to PCIE RP 5 */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NATIVE),
+	PAD_NC(GPP_D10, NATIVE),
+	PAD_NC(GPP_D11, NATIVE),
+	PAD_NC(GPP_D12, NATIVE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */
+	PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group RESERVED ------- */
+
+	PAD_NC(GPP_CPU_RSVD_1, NONE),
+	PAD_NC(GPP_CPU_RSVD_2, NONE),
+	PAD_NC(GPP_CPU_RSVD_3, NONE),
+	PAD_NC(GPP_CPU_RSVD_4, NONE),
+	PAD_NC(GPP_CPU_RSVD_5, NONE),
+	PAD_NC(GPP_CPU_RSVD_6, NONE),
+	PAD_NC(GPP_CPU_RSVD_7, NONE),
+	PAD_NC(GPP_CPU_RSVD_8, NONE),
+	PAD_NC(GPP_CPU_RSVD_9, NONE),
+	PAD_NC(GPP_CPU_RSVD_10, NONE),
+	PAD_NC(GPP_CPU_RSVD_11, NONE),
+	PAD_NC(GPP_CPU_RSVD_12, NONE),
+	PAD_NC(GPP_CPU_RSVD_13, NONE),
+	PAD_NC(GPP_CPU_RSVD_14, NONE),
+	PAD_NC(GPP_CPU_RSVD_15, NONE),
+	PAD_NC(GPP_CPU_RSVD_16, NONE),
+	PAD_NC(GPP_CPU_RSVD_17, NONE),
+	PAD_NC(GPP_CPU_RSVD_18, NONE),
+	PAD_NC(GPP_CPU_RSVD_19, NONE),
+	PAD_NC(GPP_CPU_RSVD_20, NONE),
+	/* GPP_CPU_RSVD_21 - GPP_CPU_RSVD_21 */
+	PAD_CFG_NF(GPP_CPU_RSVD_21, NONE, DEEP, NF1),
+	/* GPP_CPU_RSVD_22 - GPP_CPU_RSVD_22 */
+	PAD_CFG_NF(GPP_CPU_RSVD_22, NONE, DEEP, NF1),
+	/* GPP_CPU_RSVD_23 - GPP_CPU_RSVD_23 */
+	PAD_CFG_NF(GPP_CPU_RSVD_23, NONE, DEEP, NF1),
+	/* GPP_CPU_RSVD_24 - GPP_CPU_RSVD_24 */
+	PAD_CFG_NF(GPP_CPU_RSVD_24, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group vGPIO ------- */
+
+	/* GPP_VGPIO_0 - GPIO */
+	PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP),
+	/* GPP_VGPIO_4 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI),
+	/* GPP_VGPIO_5 - GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI),
+	/* GPP_VGPIO_6 - GPP_VGPIO_6 */
+	PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1),
+	/* GPP_VGPIO_7 - GPP_VGPIO_7 */
+	PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1),
+	/* GPP_VGPIO_8 - GPP_VGPIO_8 */
+	PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1),
+	/* GPP_VGPIO_9 - GPP_VGPIO_9 */
+	PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1),
+	/* GPP_VGPIO_10 - GPP_VGPIO_10 */
+	PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1),
+	/* GPP_VGPIO_11 - GPP_VGPIO_11 */
+	PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1),
+	/* GPP_VGPIO_12 - GPP_VGPIO_12 */
+	PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1),
+	/* GPP_VGPIO_13 - GPP_VGPIO_13 */
+	PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1),
+	/* GPP_VGPIO_18 - GPP_VGPIO_18 */
+	PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1),
+	/* GPP_VGPIO_19 - GPP_VGPIO_19 */
+	PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1),
+	/* GPP_VGPIO_20 - GPP_VGPIO_20 */
+	PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1),
+	/* GPP_VGPIO_21 - GPP_VGPIO_21 */
+	PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1),
+	/* GPP_VGPIO_22 - GPP_VGPIO_22 */
+	PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1),
+	/* GPP_VGPIO_23 - GPP_VGPIO_23 */
+	PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1),
+	/* GPP_VGPIO_24 - GPP_VGPIO_24 */
+	PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1),
+	/* GPP_VGPIO_25 - GPP_VGPIO_25 */
+	PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1),
+	/* GPP_VGPIO_30 - GPP_VGPIO_30 */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1),
+	/* GPP_VGPIO_31 - GPP_VGPIO_31 */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1),
+	/* GPP_VGPIO_32 - GPP_VGPIO_32 */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1),
+	/* GPP_VGPIO_33 - GPP_VGPIO_33 */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1),
+	/* GPP_VGPIO_34 - GPP_VGPIO_34 */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+	/* GPP_VGPIO_35 - GPP_VGPIO_35 */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+	/* GPP_VGPIO_36 - GPP_VGPIO_36 */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+	/* GPP_VGPIO_37 - GPP_VGPIO_37 */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* ------- GPIO Group GPP_GPD ------- */
+
+	/* GPD0 - BATLOW# */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	/* GPD1 - ACPRESENT */
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	PAD_NC(GPD2, NONE),
+	/* GPD3 - PWRBTN# */
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	/* GPD4 - SLP_S3# */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	/* GPD5 - SLP_S4# */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	/* GPD6 - SLP_A# */
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_NC(GPD7, NONE),
+	PAD_NC(GPD8, NONE),
+	PAD_NC(GPD9, NONE),
+	/* GPD10 - SLP_S5# */
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_NC(GPD11, NONE),
+	/* GPD_INPUT3VSEL - GPD_INPUT3VSEL */
+	PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1),
+	/* GPD_SLP_LANB - GPD_SLP_LANB */
+	PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1),
+	/* GPD_SLP_SUSB - GPD_SLP_SUSB */
+	PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1),
+	/* GPD_WAKEB - GPD_WAKEB */
+	PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1),
+	/* GPD_DRAM_RESETB - GPD_DRAM_RESETB */
+	PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1),
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+
+	/* GPP_C0 - SMBCLK */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	/* GPP_C1 - SMBDATA */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	/* GPP_C2 - GPIO */
+	PAD_CFG_GPO(GPP_C2, 0, DEEP),
+	/* GPP_C3 - SML0CLK */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	/* GPP_C4 - SML0DATA */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	/* GPP_C5 - GPIO */
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	/* GPP_C6 - SML1CLK */
+	PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1),
+	/* GPP_C7 - SML1DATA */
+	PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1),
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_NC(GPP_C16, NONE),
+	PAD_NC(GPP_C17, NONE),
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+
+	PAD_NC(GPP_F0, NONE),
+	PAD_NC(GPP_F1, NONE),
+	PAD_NC(GPP_F2, NONE),
+	PAD_NC(GPP_F3, NONE),
+	PAD_NC(GPP_F4, NONE),
+	PAD_NC(GPP_F5, NONE),
+	PAD_NC(GPP_F6, NONE),
+	PAD_NC(GPP_F7, NONE),
+	PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	/* TODO: how this ON/OFF should be configured and handled by OS? */
+	/* GPP_F15 - GPIO, ON/OFF signal for M.2 LTE */
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F20 - Reserved */
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	/* GPP_F21 - Reserved */
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+	/* GPP_F_CLK_LOOPBK - GPIO */
+	PAD_NC(GPP_F_CLK_LOOPBK, NONE),
+
+	/* ------- GPIO Group GPP_HVCMOS ------- */
+
+	PAD_NC(GPP_L_BKLTEN, NONE),
+	PAD_NC(GPP_L_BKLTCTL, NONE),
+	PAD_NC(GPP_L_VDDEN, NONE),
+	/* GPP_SYS_PWROK - n/a */
+	PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1),
+	/* GPP_SYS_RESETB - n/a */
+	PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1),
+	/* GPP_MLK_RSTB - n/a */
+	PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group GPP_E ------- */
+
+	PAD_NC(GPP_E0, NONE),
+	PAD_NC(GPP_E1, NONE),
+	/* GPP_E2 - TYPE_C_PD_IRQ */
+	PAD_CFG_GPI_APIC_LOW(GPP_E2, NONE, PLTRST),
+	PAD_NC(GPP_E3, NONE),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE),
+	PAD_NC(GPP_E7, NONE),
+	PAD_NC(GPP_E8, NONE),
+	PAD_NC(GPP_E9, NONE),
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E12, NONE),
+	/* GPP_E13 - TPM_PIRQ# */
+	PAD_CFG_GPI_APIC_LOW(GPP_E13, NONE, PLTRST),
+	/* GPP_E14 - DDSP_HPDA */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* GPP_E15 - Reserved */
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2),
+	/* GPP_E16 - Reserved */
+	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE),
+	PAD_NC(GPP_E20, NATIVE),
+	PAD_NC(GPP_E21, NATIVE),
+	/* GPP_E22 - DDPA_CTRLCLK */
+	PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1),
+	/* GPP_E23 - DDPA_CTRLDATA */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+	/* GPP_E_CLK_LOOPBK - GPIO */
+	PAD_NC(GPP_E_CLK_LOOPBK, NONE),
+
+	/* ------- GPIO Community 5 ------- */
+
+	/* ------- GPIO Group GPP_R ------- */
+
+	PAD_NC(GPP_R0, NONE),
+	PAD_NC(GPP_R1, NATIVE),
+	PAD_NC(GPP_R2, NATIVE),
+	PAD_NC(GPP_R3, NATIVE),
+	PAD_NC(GPP_R4, NONE),
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE)
+};
+
+const struct pad_config *board_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
diff --git a/src/mainboard/protectli/vault_adl_p/gpio.h b/src/mainboard/protectli/vault_adl_p/gpio.h
new file mode 100644
index 0000000000..e2c63ae082
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+const struct pad_config *board_gpio_table(size_t *num);
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/protectli/vault_adl_p/hda_verb.c b/src/mainboard/protectli/vault_adl_p/hda_verb.c
new file mode 100644
index 0000000000..a8a40ed595
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/hda_verb.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Alderlake-P HDMI */
+	0x8086281c, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	7, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	0x00278111,
+	0x00278111,
+	0x00278111,
+	0x00278111,
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560030),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560040),
+	0x00278100,
+	0x00278100,
+	0x00278100,
+	0x00278100
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/protectli/vault_adl_p/mainboard.c b/src/mainboard/protectli/vault_adl_p/mainboard.c
new file mode 100644
index 0000000000..eef2ff9a0e
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/mainboard.c
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <cpu/x86/name.h>
+#include <delay.h>
+#include <device/device.h>
+#include <intelblocks/systemagent.h>
+#include <smbios.h>
+#include <soc/ramstage.h>
+#include <soc/pcr_ids.h>
+#include <soc/tcss.h>
+#include <string.h>
+
+#include "board_beep.h"
+
+const char *smbios_mainboard_product_name(void)
+{
+	char processor_name[49];
+
+	fill_processor_name(processor_name);
+
+	if (strstr(processor_name, "i3-1215U") != NULL)
+		return "VP6630";
+	else if (strstr(processor_name, "i5-1235U") != NULL)
+		return "VP6650";
+	else if (strstr(processor_name, "i7-1255U") != NULL)
+		return "VP6670";
+	else
+		return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME;
+}
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	int i;
+
+	memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm));
+	memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+
+	memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm));
+	memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating));
+	memset(params->CpuPciePowerGating, 0, sizeof(params->CpuPciePowerGating));
+	memset(params->CpuPcieRpPmSci, 0, sizeof(params->CpuPcieRpPmSci));
+
+	/* Max payload 256B */
+	memset(params->PcieRpMaxPayload, 1, sizeof(params->PcieRpMaxPayload));
+
+	/* CLKREQs connected only to RP5 and RP6 */
+	params->PcieRpEnableCpm[4] = 1;
+	params->PcieRpEnableCpm[5] = 1;
+
+	/* Type-C PD */
+	params->PmcPdEnable = 1;
+	params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; /* GPP_H6 */
+	params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; /* GPP_H7 */
+	params->PortResetMessageEnable[7] = 1;
+
+	/* IOM USB config */
+	params->PchUsbOverCurrentEnable = 0;
+
+	params->EnableTcssCovTypeA[0] = 1;
+	params->EnableTcssCovTypeA[1] = 1;
+	params->EnableTcssCovTypeA[3] = 1;
+
+	params->MappingPchXhciUsbA[0] = 1;
+	params->MappingPchXhciUsbA[1] = 2;
+	params->MappingPchXhciUsbA[3] = 4;
+
+	params->CnviRfResetPinMux = 0;
+	params->CnviClkreqPinMux = 0;
+
+	/*
+	 * Workaround: poll for IOM ready before SiliconInit for 2 seconds. ME
+	 * seems to be too sluggish with its firmware initialization and IOM
+	 * is not ready during TCSS Init in SiliconInit, when serial console
+	 * debugging is disabled in coreboot. Entering FSP SiliconInit without
+	 * IOM ready, will cause the XHCI controller in the CPU to be disabled
+	 * and all USB 3.x ports on the platform non-functional.
+	 */
+	for (i = 0; i < 200; i++) {
+		if (REGBAR32(PID_IOM, IOM_TYPEC_STATUS_1) & IOM_READY)
+			return;
+
+		mdelay(10);
+	}
+
+	printk(BIOS_ERR, "TCSS IOM not ready, USB3.0 ports will not be functional\n");
+}
+
+static void mainboard_final(void *chip_info)
+{
+	if (CONFIG(BEEP_ON_BOOT))
+		do_beep(1500, 100);
+}
+
+struct chip_operations mainboard_ops = {
+	.final = mainboard_final,
+};
diff --git a/src/mainboard/protectli/vault_adl_p/romstage_fsp_params.c b/src/mainboard/protectli/vault_adl_p/romstage_fsp_params.c
new file mode 100644
index 0000000000..5f3606c146
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/romstage_fsp_params.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+#include <soc/gpio.h>
+
+#include "gpio.h"
+
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+	.ect = true, /* Early Command Training */
+	.UserBd = BOARD_TYPE_MOBILE,
+	.LpDdrDqDqsReTraining = 1,
+};
+
+static const struct mem_spd dimm_module_spd_info = {
+	.topo = MEM_TOPO_DIMM_MODULE,
+	.smbus = {
+		[0] = {
+			.addr_dimm[0] = 0x50,
+		},
+		[1] = {
+			.addr_dimm[0] = 0x52,
+		},
+	},
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false);
+
+	pads = board_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+	memupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 0;
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 0;
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0;
+
+	/* Limit the max speed for memory compatibility */
+	memupd->FspmConfig.DdrFreqLimit = 4200;
+}
diff --git a/src/mainboard/protectli/vault_adl_p/vboot-rwa.fmd b/src/mainboard/protectli/vault_adl_p/vboot-rwa.fmd
new file mode 100644
index 0000000000..65b52d97f5
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_p/vboot-rwa.fmd
@@ -0,0 +1,38 @@
+FLASH@0xff000000 16M {
+	SI_ALL@0x0 {
+		SI_DESC 4K
+		SI_ME 0x4c0000
+		SI_DEVICEEXT2 0xbf000
+	}
+	SI_BIOS@0x580000 0xa80000 {
+		SMMSTORE(PRESERVE) 256K
+
+		RW_MISC 320K {
+			UNIFIED_MRC_CACHE(PRESERVE) {
+				RECOVERY_MRC_CACHE 128K
+				RW_MRC_CACHE 128K
+			}
+			RW_VPD(PRESERVE) 8K
+			RW_NVRAM(PRESERVE) 24K
+		}
+
+		BOOTSPLASH(CBFS) 512K
+
+		RW_SECTION_A {
+			VBLOCK_A 64K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 0x100
+		}
+
+		WP_RO 5M {
+			RO_VPD(PRESERVE) 16K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 0x100
+				RO_FRID_PAD 0x700
+				GBB 12K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}