diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-01 19:08:47 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-10 10:16:57 +0000 |
| commit | 23d5c4c532f5b3c405cae7389702042b44a0247b (patch) | |
| tree | 1b97102bbfcb261e79e38be0daf6ac6937abe85b /src/mainboard | |
| parent | dad7f37f729cee52c8839e18803042e5cf2309c7 (diff) | |
mb/asus/p8h61-m_pro: Make devicetree prettier
Replace a bunch of spaces with tabs, put host bridge and friends above
southbridge, fix "TPM Module" (Trusted Platform Module Module) and add
some empty lines to help the reader.
Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/asus/p8h61-m_pro/devicetree.cb | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index 166a625a82..ee9a0fc45c 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -30,13 +30,18 @@ chip northbridge/intel/sandybridge end register "pci_mmio_size" = "2048" device domain 0x0 on - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) + device pci 02.0 on end # Internal graphics VGA controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" - register "gen1_dec" = "0x000c0291" # HWM + register "gen1_dec" = "0x000c0291" # HWM register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -46,8 +51,8 @@ chip northbridge/intel/sandybridge device pci 1b.0 on end # High Definition Audio Audio controller device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) - device pci 1c.2 on # Realtek RTL8111E Ethernet Controller - chip drivers/net + device pci 1c.2 on # Realtek RTL8111E Ethernet Controller + chip drivers/net register "customized_leds" = "0x00f6" register "wake" = "9" device pci 00.0 on end @@ -113,16 +118,13 @@ chip northbridge/intel/sandybridge end end chip drivers/pc80/tpm - device pnp 4e.0 on end # TPM module + device pnp 4e.0 on end # TPM end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) - device pci 02.0 on end # Internal graphics VGA controller end end |