x60,t60,x201,macbook21 : Declare GPIs for EC

For lenovo/x201, this also changes GPI_ROUT (0xb8-0xbb)
programming to use GPI1 between SCI/SMI modes, while
previous programming was for GPI12.

Change-Id: I3ac0feaa1d10c8f0e53a5fa5af72366503bb5d2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8656
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

4 files changed, 23 insertions, 14 deletions

diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c
index 449e36777e..f90bb38336 100644
--- a/src/mainboard/apple/macbook21/smihandler.c
+++ b/src/mainboard/apple/macbook21/smihandler.c
@@ -27,6 +27,8 @@
 #include <pc80/mc146818rtc.h>
 #include <delay.h>
 
+#define GPE_EC_SCI	12
+
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
  */
@@ -69,7 +71,7 @@ int mainboard_smi_apmc(u8 data)
 	switch(data) {
 		case APM_CNT_ACPI_ENABLE:
 			/* route H8SCI to SCI */
-			outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+			outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
 			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
 			tmp &= ~0x03;
 			tmp |= 0x02;
@@ -77,7 +79,7 @@ int mainboard_smi_apmc(u8 data)
 			break;
 		case APM_CNT_ACPI_DISABLE:
 			/* route H8SCI# to SMI */
-			outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+			outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
 			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
 			tmp &= ~0x03;
 			tmp |= 0x01;
diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c
index 36495dc0d8..3833ae24ff 100644
--- a/src/mainboard/lenovo/t60/smihandler.c
+++ b/src/mainboard/lenovo/t60/smihandler.c
@@ -28,6 +28,8 @@
 #include "dock.h"
 #include "smi.h"
 
+#define GPE_EC_SCI	12
+
 #define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
@@ -154,7 +156,7 @@ static void mainboard_smi_handle_ec_sci(void)
 
 void mainboard_smi_gpi(u32 gpi)
 {
-	if (gpi & (1 << 12))
+	if (gpi & (1 << GPE_EC_SCI))
 		mainboard_smi_handle_ec_sci();
 }
 
@@ -173,7 +175,7 @@ int mainboard_smi_apmc(u8 data)
 			/* use 0x1600/0x1604 to prevent races with userspace */
 			ec_set_ports(0x1604, 0x1600);
 			/* route H8SCI to SCI */
-			outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+			outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
 			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
 			tmp &= ~0x03;
 			tmp |= 0x02;
@@ -184,7 +186,7 @@ int mainboard_smi_apmc(u8 data)
 			   provide a EC query function */
 			ec_set_ports(0x66, 0x62);
 			/* route H8SCI# to SMI */
-			outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+			outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
 			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
 			tmp &= ~0x03;
 			tmp |= 0x01;
diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c
index d8e78072fd..7b14191683 100644
--- a/src/mainboard/lenovo/x201/smihandler.c
+++ b/src/mainboard/lenovo/x201/smihandler.c
@@ -34,6 +34,9 @@
 #include "dock.h"
 #include "smi.h"
 
+#define GPE_EC_SCI	1
+#define GPE_EC_WAKE	13
+
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
  */
@@ -137,7 +140,7 @@ static void mainboard_smi_handle_ec_sci(void)
 
 void mainboard_smi_gpi(u32 gpi_sts)
 {
-	if (gpi_sts & (1 << 1))
+	if (gpi_sts & (1 << GPE_EC_SCI))
 		mainboard_smi_handle_ec_sci();
 }
 
@@ -173,7 +176,7 @@ int mainboard_smi_apmc(u8 data)
 		/* use 0x1600/0x1604 to prevent races with userspace */
 		ec_set_ports(0x1604, 0x1600);
 		/* route H8SCI to SCI */
-		outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+		outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
 		tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
 		tmp &= ~0x03;
 		tmp |= 0x02;
@@ -186,7 +189,7 @@ int mainboard_smi_apmc(u8 data)
 		   provide a EC query function */
 		ec_set_ports(0x66, 0x62);
 		/* route H8SCI# to SMI */
-		outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+		outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI),
 		     pmbase + ALT_GP_SMI_EN);
 		tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
 		tmp &= ~0x03;
@@ -211,11 +214,11 @@ void mainboard_smi_sleep(u8 slp_typ)
 			u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
 
 			/* Enable EC WAKE GPE.  */
-			outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN);
+			outl(inl(pmbase + GPE0_EN) | (1 << (16 + GPE_EC_WAKE)), pmbase + GPE0_EN);
 			gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
 			/* Redirect EC WAKE GPE to SCI.  */
-			gpe_rout &= ~(3 << 26);
-			gpe_rout |= (2 << 26);
+			gpe_rout &= ~(3 << (2 * GPE_EC_WAKE));
+			gpe_rout |= (2 << (2 * GPE_EC_WAKE));
 			pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
 		}
 	}
diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c
index ccc328e26e..fee54f266a 100644
--- a/src/mainboard/lenovo/x60/smihandler.c
+++ b/src/mainboard/lenovo/x60/smihandler.c
@@ -31,6 +31,8 @@
 #include "dock.h"
 #include "smi.h"
 
+#define GPE_EC_SCI	12
+
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
  */
@@ -160,7 +162,7 @@ static void mainboard_smi_handle_ec_sci(void)
 
 void mainboard_smi_gpi(u32 gpi)
 {
-	if (gpi & (1 << 12))
+	if (gpi & (1 << GPE_EC_SCI))
 		mainboard_smi_handle_ec_sci();
 }
 
@@ -179,7 +181,7 @@ int mainboard_smi_apmc(u8 data)
 			/* use 0x1600/0x1604 to prevent races with userspace */
 			ec_set_ports(0x1604, 0x1600);
 			/* route H8SCI to SCI */
-			outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+			outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
 			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
 			tmp &= ~0x03;
 			tmp |= 0x02;
@@ -192,7 +194,7 @@ int mainboard_smi_apmc(u8 data)
 			   provide a EC query function */
 			ec_set_ports(0x66, 0x62);
 			/* route H8SCI# to SMI */
-			outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+			outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
 			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
 			tmp &= ~0x03;
 			tmp |= 0x01;