diff options
| author | zbao <fishbaozi@gmail.com> | 2015-11-05 20:25:59 +0800 |
|---|---|---|
| committer | Zheng Bao <zheng.bao@amd.com> | 2015-11-06 07:53:00 +0100 |
| commit | 1897c2c3508f3d5e2d020c6e56f16611c8cfad4a (patch) | |
| tree | c3c938dec8e37d0375a791bb96f38fd7aa963fad /src/mainboard | |
| parent | aeb2103ab5184d46dc315f616acbf521f3aa1ab4 (diff) | |
AMD Bettong: Enable S4 feature for Windows 7
PMIOxEE is for setting USB3 power rail. Set it to S0, otherwise
going into hibernation can not be wake up.
Change-Id: I692497bad24d745738d670897e725a568c1db114
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11373
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/bettong/romstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 9f94d7b6c5..6399804ac2 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <arch/acpi.h> +#include <arch/io.h> #include <arch/stages.h> #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> @@ -78,6 +79,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) prepare_for_resume(); } + if (s3resume || acpi_is_wakeup_s4()) { + outb(0xEE, PM_INDEX); + outb(0x8, PM_DATA); + } + post_code(0x50); copy_and_run(); |