diff options
| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2019-09-12 13:43:18 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-09-14 05:47:59 +0000 |
| commit | 15b0ab51b9d73f0c7669a367c181dedd675ea6d0 (patch) | |
| tree | f3155296b080becefc28fd96e3dbc02ece3779ff /src/mainboard | |
| parent | afd7ce680be5a3efd170cc4ce4e4be7f5d27d61e (diff) | |
mb/asrock/h110m: configure GPIOs in SuperIO chip
Enables and configures GPIOs in the NCT6791D chip. The values for
registers taken from the superiotool dump.
Change-Id: I5968a6c20cc013697d64bfbe4fc2e7b2390b72b0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/asrock/h110m/devicetree.cb | 39 |
1 files changed, 30 insertions, 9 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 9552b10f0a..88a4edc047 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -353,18 +353,39 @@ chip soc/intel/skylake irq 0x72 = 12 # Mouse end device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6 - device pnp 2e.107 off end # GPIO7 - device pnp 2e.207 off end # GPIO8 + device pnp 2e.7 on # GPIO6 + irq 0xf6 = 0xff + irq 0xf7 = 0xff + irq 0xf8 = 0xff + end + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x7f + irq 0xe1 = 0x0d + end + device pnp 2e.207 on # GPIO8 + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xed = 0xff + end device pnp 2e.8 off end # WDT - device pnp 2e.108 off end # GPIO0 + device pnp 2e.108 on end # GPIO0 device pnp 2e.308 off end # GPIO base device pnp 2e.408 off end # WDTMEM - device pnp 2e.708 off end # GPIO1 - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 off end # GPIO3 - device pnp 2e.209 off end # GPIO4 - device pnp 2e.309 off end # GPIO5 + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x7b + irq 0xe5 = 0x02 + irq 0xea = 0x04 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xf1 = 0x80 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0xd5 + end device pnp 2e.a on # Power RAM in S3 and let the PCH # handle power failure actions |